SMSC LAN9311 User Manual

SMSC LAN9311/LAN9311i

Revision 1.4 (08-19-08) 

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High performance and full featured 2 port switch with 

VLAN, QoS packet prioritization, Rate Limiting, IGMP 
Snooping and management functions 

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Easily interfaces to most 16-bit embedded CPU’s

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Unique Virtual PHY feature simplifies software 

development by mimicking the multiple switch ports 
as a single port MAC/PHY

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Integrated IEEE 1588 Hardware Time Stamp Unit

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Cable, satellite, and IP set-top boxes

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Digital televisions

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Digital video recorders

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VoIP/Video phone systems

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Home gateways

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Test/Measurement equipment

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Industrial automation systems

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Ethernet Switch Fabric

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32K buffer RAM

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1K entry forwarding table

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Port based IEEE 802.1Q VLAN support (16 groups)

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Programmable IEEE 802.1Q tag insertion/removal

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IEEE 802.1d spanning tree protocol support

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QoS/CoS Packet prioritization

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4 dynamic QoS queues per port

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Input priority determined by VLAN tag, DA lookup, 
TOS, DIFFSERV or port default value

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Programmable class of service map based on input 
priority

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Remapping of 802.1Q priority field on per port basis

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Programmable rate limiting at the ingress/egress 
ports with random early discard, per port / priority

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IGMP v1/v2/v3 snooping for Multicast packet filtering

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IPV6 Multicast Listener Discovery snoop

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Programmable filter by MAC address

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Switch Management

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Port mirroring/monitoring/sniffing: ingress and/or egress 
traffic on any ports or port pairs

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Fully compliant statistics (MIB) gathering counters

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Control registers configurable on-the-fly

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Ports

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2 internal 10/100 PHYs with HP Auto-MDIX support

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Fully compliant with IEEE 802.3 standards

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10BASE-T and 100BASE-TX support

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Full and half duplex support

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Full duplex flow control

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Backpressure (forced collision) half duplex flow control

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Automatic flow control based on programmable levels 

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Automatic 32-bit CRC generation and checking

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Automatic payload padding

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2K Jumbo packet support

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Programmable interframe gap, flow control pause value

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Full transmit/receive statistics

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Auto-negotiation

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Automatic MDI/MDI-X

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Loop-back mode

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High-performance host bus interface

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Provides in-band network communication path

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Access to management registers

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Simple, SRAM-like interface

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16-bit data bus

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Big, little, and mixed endian support

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Large TX and RX FIFO’s for high latency applications

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Programmable water marks and threshold levels

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Host interrupt support

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IEEE 1588 Hardware Time Stamp Unit

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Global 64-bit tunable clock

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Master or slave mode per port

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Time stamp on TX or RX of Sync and Delay_req 
packets per port, Timestamp on GPIO

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64-bit timer comparator event generation (GPIO or IRQ)

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Comprehensive Power Management Features

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Wake on LAN

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Wake on link status change (energy detect)

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Magic packet wakeup

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Wakeup indicator event signal

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Other Features

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General Purpose Timer

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Serial EEPROM interface (I

2

C master or Microwire

TM

 

master) for non-managed configuration

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Programmable GPIOs/LEDs

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Single 3.3V power supply

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Available in Commercial & Industrial Temp. Ranges