Fujitsu CM71-00101-5E User Manual
80
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.9
SUBC (Subtract Word Data in Source Register and Carry
Bit from Destination Register)
Bit from Destination Register)
Subtracts the word data in "Rj" and the carry bit from the word data in "Ri", stores
results to "Ri".
results to "Ri".
■
SUBC (Subtract Word Data in Source Register and Carry Bit from Destination
Register)
Register)
Assembler format:
SUBC Rj, Ri
Operation:
Ri – Rj – C
→
Ri
Flag change:
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a borrow has occurred as a result of the operation, cleared otherwise.
Execution cycles:
1 cycle
Instruction format:
Example:
SUBC R2, R3
N
Z
V
C
C
C
C
C
MSB
LSB
1
0
1
0
1
1
0
1
Rj
Ri
R2
R3
1 2 3 4
5 6 7 8
9 9 9 9
9 9 9 9
N Z V C
CCR
R2
R3
CCR
0 0 0 1
N Z V C
1 0 0 0
8 7 6 5
4 3 2 0
1 2 3 4
5 6 7 8
Before execution
After execution
Instruction bit pattern : 1010 1101 0010 0011