Fujitsu CM71-00101-5E User Manual
90
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.17
ANDB (And Byte Data of Source Register to Data in
Memory)
Memory)
Takes the logical AND of the byte data at memory address "Ri" and the byte data in "Rj",
stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■
ANDB (And Byte Data of Source Register to Data in Memory)
Assembler format:
ANDB Rj, @Ri
Operation:
(Ri) and Rj
→
(Ri)
Flag change:
N:
Set when the MSB (bit 7) of the operation result is "1", cleared when the MSB is "0".
Z:
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
1 + 2a cycles
Instruction format:
N
Z
V
C
C
C
–
–
MSB
LSB
1
0
0
0
0
1
1
0
Rj
Ri