Fujitsu CM71-00101-5E User Manual
119
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.33
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at
memory address "Ri", places the results in the condition code register (CCR).
memory address "Ri", places the results in the condition code register (CCR).
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BTSTH (Test Higher 4 Bits of Byte Data in Memory)
Assembler format:
BTSTH #u4, @Ri
Operation:
{u4 < < 4} and (Ri) [Test uses higher 4 bits only]
Flag change:
N:
Set when the MSB (bit 7) of the operation result is "1", cleared when the MSB is "0".
Z:
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
2 + a cycles
Instruction format:
Example:
BTSTH #1, @R3
N
Z
V
C
C
C
–
–
MSB
LSB
1
0
0
0
1
0
0
1
u4
Ri
12345678
12345679
1 2 3 4
5 6 7 8
N Z V C
CCR
R3
R3
CCR
0 0 0 0
0 1
N Z V C
0 1 0 0
1 2 3 4
5 6 7 8
12345678
12345679
0 1
Instruction bit pattern :
1000 1001 0001 0011
Before execution
After execution
Memory
Memory