Fujitsu CM71-00101-5E User Manual
128
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.38
DIV0S (Initial Setting Up for Signed Division)
This command is used for signed division in which the multiplication/division register
(MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the
"MDL" and the remainder in the multiplication/division register (MDH).
The value of the sign bit in the "MDL" and "Ri" is used to set the "D0" and "D1" flag bits
in the system condition code register (SCR).
• D0: Set when the dividend is negative, cleared when positive.
• D1: Set when the divisor and dividend signs are different, cleared when equal.
The word data in the "MDL" is extended to 64 bits, with the higher word in the "MDH"
and the lower word in the "MDL".
To execute signed division, the following instructions are used in combination.
DIV0S, DIV1×32, DIV2, DIV3, DIV4S
(MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the
"MDL" and the remainder in the multiplication/division register (MDH).
The value of the sign bit in the "MDL" and "Ri" is used to set the "D0" and "D1" flag bits
in the system condition code register (SCR).
• D0: Set when the dividend is negative, cleared when positive.
• D1: Set when the divisor and dividend signs are different, cleared when equal.
The word data in the "MDL" is extended to 64 bits, with the higher word in the "MDH"
and the lower word in the "MDL".
To execute signed division, the following instructions are used in combination.
DIV0S, DIV1×32, DIV2, DIV3, DIV4S
■
DIV0S (Initial Setting Up for Signed Division)
Assembler format:
DIV0S Ri
Operation:
MDL [31]
→
D0
MDL [31] eor Ri [31]
→
D1
exts (MDL)
→
MDH, MDL
Flag change:
N, Z, V, and C: Unchanged
Execution cycles:
1 cycle
Instruction format:
N
Z
V
C
–
–
–
–
MSB
LSB
1
0
0
1
0
1
1
1
0
1
0
0
Ri