Fujitsu CM71-00101-5E User Manual
190
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.92
INTE (Software Interrupt for Emulator)
This software interrupt instruction is used for debugging. It stores the values of the
program counter (PC) and program status (PS) to the stack indicated by the system
stack pointer (SSP) for interrupt processing. It writes "0" to the "S" flag in the condition
code register (CCR), and uses the "SSP" as the stack pointer for the following steps.
It determines the branch destination address by reading interrupt vector number "#9"
from the vector table, then branches.
There is no change to the "I" flag in the condition code register (CCR).
The interrupt level mask register (ILM) in the program status (PS) is set to level 4.
This instruction is the software interrupt instruction for debugging.
In step execution, no "EIT" events are generated by the "INTE" instruction.
This instruction has no delay slot.
program counter (PC) and program status (PS) to the stack indicated by the system
stack pointer (SSP) for interrupt processing. It writes "0" to the "S" flag in the condition
code register (CCR), and uses the "SSP" as the stack pointer for the following steps.
It determines the branch destination address by reading interrupt vector number "#9"
from the vector table, then branches.
There is no change to the "I" flag in the condition code register (CCR).
The interrupt level mask register (ILM) in the program status (PS) is set to level 4.
This instruction is the software interrupt instruction for debugging.
In step execution, no "EIT" events are generated by the "INTE" instruction.
This instruction has no delay slot.
■
INTE (Software Interrupt for Emulator)
Assembler format:
INTE
Operation:
SSP – 4
→
SSP
PS
→
(SSP)
SSP – 4
→
SSP
PC + 2
→
(SSP)
4
→
ILM
"0"
→
S flag
(TBR + 3D8
H
)
→
PC
Flag change:
I, N, Z, V, and C: Unchanged
S:
Cleared to "0".
Execution cycles: 3 + 3a cycles
Instruction format:
S
I
N
Z
V
C
0
–
–
–
–
–
MSB
LSB
1
0
0
1
1
1
1
1
0
0
1
1
0
0
0
0