Fujitsu CM71-00101-5E User Manual
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CHAPTER 1 FR FAMILY OVERVIEW
1.1
Features of the FR Family CPU Core
The FR family CPU core features proprietary Fujitsu architecture and is designed for
controller applications using 32-bit "RISC" based computing. The architecture is
optimized for use in microcontroller CPU cores for built-in control applications where
high-speed control is required.
controller applications using 32-bit "RISC" based computing. The architecture is
optimized for use in microcontroller CPU cores for built-in control applications where
high-speed control is required.
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Features of the FR Family CPU Core
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General-purpose register architecture
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Linear space for 32-bit (4 Gbytes) addressing
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16-bit fixed instruction length (excluding immediate data, coprocessor instructions)
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5-stage pipeline configuration for basic instructions, one-instruction one-cycle execution
•
32-bit by 32-bit computation enables completion of multiplication instructions within five cycles
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Stepwise division instructions enable 32-bit/ 32-bit division
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Direct addressing instructions for peripheral circuit access
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Coprocessor instructions for direct designation of peripheral accelerator
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High speed interrupt processing complete within 6 cycles