Fujitsu CM71-00101-5E User Manual

286

Interrupt Level Mask Register (ILM: Bit 20 to bit 16)

LD (Load Word Data in Memory to Program Status 

Register)

Note on PS Register

Overview of the Multiplication/Division Register

Overview of the Table Base Register

Precautions Related to the Table Base Register

STILM (Set Immediate Data to Interrupt Level Mask 

Register)

System Condition Code Register (SCR: Bit 10 to 

bit 08)

Table Base Register Configuration

Table Base Register Functions

Register Bypassing

Register Bypassing

Register Hazards

Overview of Register Hazards

Remainder

DIV2 (Correction when Remainder is 0)

DIV3 (Correction when Remainder is 0)

Reset

Initialization of CPU Internal Register Values at Reset

Reset Operations

Reset Priority Level

Restoring

Saving and Restoring Coprocessor Error Information

Restrictions

Data Restrictions on Word Alignment

Program Restrictions on Word Alignment

Restrictions on Interrupts during Processing of 

Delayed Branching Instructions

RET

RET (Return from Subroutine)

RET:D (Return from Subroutine)

RETI

RETI (Return from Interrupt)

Return Pointer

Overview of the Return Pointer

Return Pointer Configuration

Return Pointer Functions

Right Direction

ASR (Arithmetic Shift to the Right Direction)

.................................................. 144, 145

ASR2 (Arithmetic Shift to the Right Direction)

LSR (Logical Shift to the Right Direction)

.................................................. 141, 142

LSR2 (Logical Shift to the Right Direction)

Sample

Sample Configuration of an FR Family Device

Sample Configuration of the FR Family CPU

Save

COPSV (Save 32-bit Data from Coprocessor Register 

to Register)

Saving

Saving and Restoring Coprocessor Error Information

SCR

System Condition Code Register (SCR: Bit 10 to 

bit 08)

Set Immediate Data

STILM (Set Immediate Data to Interrupt Level Mask 

Sign Extend

EXTSB (Sign Extend from Byte Data to Word Data)

EXTSH (Sign Extend from Byte Data to Word Data)

Signed Division

DIV0S (Initial Setting Up for Signed Division)

DIV4S (Correction Answer for Signed Division)

Simultaneous Occurrences

Priority of Simultaneous Occurrences

Software Interrupt

INT (Software Interrupt)

INTE (Software Interrupt for Emulator)

Source Register

ADD (Add Word Data of Source Register to 

Destination Register)

ADDC (Add Word Data of Source Register and Carry 

Bit to Destination Register)

ADDN (Add Word Data of Source Register to 

Destination Register)

AND (And Word Data of Source Register to Data in 

AND (And Word Data of Source Register to 

Destination Register)

ANDB (And Byte Data of Source Register to Data in 

ANDH (And Half-word Data of Source Register to 

Data in Memory)

CMP (Compare Immediate Data of Source Register 

and Destination Register)

CMP (Compare Word Data in Source Register and 

Destination Register)

EOR (Exclusive Or Word Data of Source Register to 

Data in Memory)

EOR (Exclusive Or Word Data of Source Register to 

Destination Register)