Fujitsu CM71-00101-5E User Manual

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CHAPTER 4  RESET AND "EIT" PROCESSING

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User interrupts originate as requests from peripheral circuits.

Each interrupt request is assigned an interrupt level, and it is possible to mask requests according to their

level values. Also, it is possible to disable all interrupts by using the I flag in the condition code register

(CCR) in the program status (PS).

It is possible to enter an interrupt signal through a signal pin, but in virtually all cases the interrupt

originates from the peripheral circuits contained on the FR family microcontroller chip itself.

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The CPU accepts user interrupts when the following conditions are met:

•

The peripheral circuit is operating and generates an interrupt request.

•

The interrupt enable bit in the peripheral circuit’s control register is set to "enable".

•

The value of the interrupt request (ICR

*1

) is lower than the value of the ILM

*2

 setting.

•

The "I" flag is set to "1".

*1:  ICR = Interrupt Control Register ...a register on the microcontroller that controls interrupts

*2: ILM = Interrupt Level Mask Register ... a register in the CPU’s program status (PS)

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The following operating sequence takes place after a user interrupt is accepted.

•

The contents of the program status (PS) are saved to the system stack.

•

The address of the next instruction is saved to the system stack.

•

The value of the system stack pointer (SSP) is reduced by 8.

•

The value (level) of the accepted interrupt is stored in the "ILM".

•

The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).

•

The vector address of the accepted interrupt is stored in the program counter (PC).