Fujitsu CM71-00101-5E User Manual
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.4.2
Processing Delayed Branching Instructions
The FR family CPU processes delayed branching instructions with an apparent
execution speed of 1 cycle, regardless of whether branching conditions are satisfied or
not satisfied. When branching occurs, this is one cycle faster than using
non-delayed branching instructions.
However, the apparent order of instruction processing is inverted in cases where
branching occurs.
execution speed of 1 cycle, regardless of whether branching conditions are satisfied or
not satisfied. When branching occurs, this is one cycle faster than using
non-delayed branching instructions.
However, the apparent order of instruction processing is inverted in cases where
branching occurs.
■
Examples of Processing Delayed Branching Instructions
Figure 5.4-3 shows an example of processing a delayed branching instruction when branching conditions
are satisfied.
In this example, the branch destination instruction, "ST R2,@R13" is executed after the instruction "ST
R2,@R12" in the delay slot. As a result, the branching instruction has an apparent execution speed of one
cycle. However, the instruction "ST R2,@R12" in the delay slot is executed before the branch destination
instruction "ST R2,@R13" and therefore the apparent order of processing is inverted.
Figure 5.4-3 Example: Processing a Delayed Branching Instruction (Branching Condition Satisfied)
Figure 5.4-4 shows an example of processing a delayed branching instruction when branching conditions
are not satisfied.
In this example the delay slot instruction "ST R2,@R12" is executed without being canceled. As a result,
the program is processed in the order in which it is written. The branching instruction requires an apparent
processing time of one cycle.
Figure 5.4-4 Example: Processing a Delayed Branching Instruction (Branching Conditions Not Satisfied)
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
Not canceled
IF
ID
EX
MA
WB
LD @R10, R1
LD @R11, R2
ADD R1, R3
BNE:D TestOK(branching conditions satisfied)
ST R2, @R12(delay slot instruction)
ST R2, @R13(branch destination instruction)
: PC change
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
LD @R10, R1
LD @R11, R2
ADD R1, R3
BNE:D TestOK (branching conditions not satisfied)
ST R2, @R12 (delay slot instruction)
ADD #4, R12
Not canceled