Fujitsu CM71-00101-5E User Manual
75
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.4
ADDC (Add Word Data of Source Register and Carry Bit to
Destination Register)
Destination Register)
Adds the word data in "Rj" to the word data in "Ri" and carry bit, stores results to "Ri".
■
ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)
Assembler format:
ADDC Rj, Ri
Operation:
Ri + Rj + C
→
Ri
Flag change:
N :
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z :
Set when the operation result is "0", cleared otherwise.
V :
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C :
Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles:
1 cycle
Instruction format:
Example:
ADDC R2, R3
N
Z
V
C
C
C
C
C
MSB
LSB
1
0
1
0
0
1
1
1
Rj
Ri
R2
R3
1 2 3 4
5 6 7 8
8 7 6 5
4 3 2 0
N Z V C
CCR
R2
R3
CCR
0 0 0 1
N Z V C
1 0 0 0
9 9 9 9
9 9 9 9
1 2 3 4
5 6 7 8
Before execution
After execution
Instruction bit pattern : 1010 0111 0010 0011