SMC Networks ARM720T_LH79520 User Manual

RISC, or Reduced Instruction Set Computer, is a term that is conventionally used to describe a type of microprocessor 
architecture that employs a small but highly-optimized set of instructions, rather than the large set of more specialized 
instructions often found in other types of architectures. This other type of processor is traditionally referred to as CISC, or 
Complex Instruction Set Computer. 

The early RISC processors came from research projects at Stanford and Berkeley universities in the late 1970s and early 1980s. 
These processors were designed with a similar philosophy, which has become known as RISC. The basic design architecture of 
all RISC processors has generally followed the characteristics that came from these early research projects and which can be 
summarized as follows: 
•  One instruction per clock cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is 

due to the optimization of each instruction on the CPU and a technique called pipelining. This technique allows each 
instruction to be processed in a set number of stages. This in turn allows for the simultaneous execution of a number of 
different instructions, each instruction being at a different stage in the pipeline. 

•  Load/Store machine with a large number of internal registers: The RISC design philosophy typically uses a large 

number (commonly 32) of registers. Most instructions operate on these registers, with access to memory made using a very 
limited set of Load and Store instructions. This limits the need for continuous access to slow memory for loading and storing 
data. 

•  Separate Data Memory and Instruction Memory access paths: Different stages of the pipeline perform simultaneous 

accesses to memory. This Harvard style of architecture can either be used with two completely different memory spaces, a 
single dual-port memory space or, more commonly, a single memory space with separate data and instruction caches for 
the two pipeline stages. 

Over the last 20-25 years, RISC processors have been steadily improved and optimized. In one sense, the original simplicity of 
the RISC architecture has been lost – replaced by super-scalar, multiple-pipelined hardware, often running in the gigahertz 
range. 

With the advent of low-cost, high-capacity programmable logic devices, there has been something of a resurgence in the use of 
processors with simple RISC architectures. Register-rich FPGAs, with their synchronous design requirements, have found the 
ideal match when paired with these simple pipelined processors. 

As a result, most 32-bit FPGA soft processors are adopting this approach. They could even be considered as “Retro-
processors”. 

There are a number of benefits to be gained from using soft processors on reconfigurable hardware. The following sections 
explore some of the more significant of these benefits in more detail. 

For certain specific applications, the ability to change the design once it is in the field can be a significant competitive advantage. 
Applications in general can benefit from this ability also. It allows commitment to shipping early in the development cycle. It also 
allows field testing to be used to help drive the latter part of the design cycle without requiring new “board-spins” based on the 
outcome. This is very similar to the way in which alpha, beta, pre-release and release cycles currently drive the closure of 
software products. 

The ability to update embedded software in a device in the field has long been an advantage enjoyed by designers of 
embedded systems. With FPGAs, this has now become a reality for the hardware side of the design. For end-users, this 
translates as “Field Upgradeable Hardware”. 

FPGAs offer the fastest time to market due to their programmable nature. Design problems, or feature changes, can be made 
quickly and simply by changing the FPGA design – with no changes in the board-level design. 

CR0162 (v2.0) March 10, 2008