Intel SE7501WV2 User Manual
Intel® Server Board SE7501WV2 TPS
BIOS
Revision 1.0
Intel reference number C25653-001
113
Sensors are managed by the BMC. The BMC is capable of receiving event messages from
individual sensors and logging system events. Refer to the SE7501WV2 BMC EPS for
additional information concerning BMC functions.
individual sensors and logging system events. Refer to the SE7501WV2 BMC EPS for
additional information concerning BMC functions.
6.32 SMI Handler
The SMI handler is used to handle and log system level events that are not visible to the server
management firmware. If the SMI handler control bit is disabled in Setup, SMI signals are not
generated on system errors. If enabled, the SMI handler preprocesses all system errors, even
those that are normally considered to generate an NMI. The SMI handler sends a command to
the BMC to log the event and provides the data to be logged. System events that are handled
by the BIOS generate a SMI.
management firmware. If the SMI handler control bit is disabled in Setup, SMI signals are not
generated on system errors. If enabled, the SMI handler preprocesses all system errors, even
those that are normally considered to generate an NMI. The SMI handler sends a command to
the BMC to log the event and provides the data to be logged. System events that are handled
by the BIOS generate a SMI.
6.33 PCI Bus Error
The PCI bus defines two error pins, PERR# for reporting parity errors, and SERR# for reporting
system errors. The BIOS can be instructed to enable or disable reporting PERR# and SERR#
through NMI. For a PERR#, the PCI bus master has the option to retry the offending
transaction, or to report it using SERR#. All other PCI-related errors are reported by SERR#.
SERR# is routed to NMI if bit 2 of I/O register 61 is set to 0. If SERR# is enabled in BIOS setup,
all PCI-to-PCI bridges will generate an SERR# on the primary interface whenever an SERR#
occurs on the secondary side of the bus. The same is true for PERR#s.
system errors. The BIOS can be instructed to enable or disable reporting PERR# and SERR#
through NMI. For a PERR#, the PCI bus master has the option to retry the offending
transaction, or to report it using SERR#. All other PCI-related errors are reported by SERR#.
SERR# is routed to NMI if bit 2 of I/O register 61 is set to 0. If SERR# is enabled in BIOS setup,
all PCI-to-PCI bridges will generate an SERR# on the primary interface whenever an SERR#
occurs on the secondary side of the bus. The same is true for PERR#s.
6.34 Processor Bus Error
If irrecoverable errors are encountered on the host processor bus, proper execution of the BIOS
SMI handler cannot be guaranteed. The BIOS SMI handler will record errors to the system
event log only if the system has not experienced a catastrophic failure that compromises the
integrity of the SMI handler.
SMI handler cannot be guaranteed. The BIOS SMI handler will record errors to the system
event log only if the system has not experienced a catastrophic failure that compromises the
integrity of the SMI handler.
6.35 Single-Bit ECC Error Throttling Prevention
The system detects, corrects, and logs correctable errors as long as these errors occur
infrequently (the system should continue to operate without a problem).
infrequently (the system should continue to operate without a problem).
Occasionally, correctable errors are caused by a persistent failure of a single component.
Although these errors are correctable, continual calls to the error logger can throttle the system,
preventing further useful work.
Although these errors are correctable, continual calls to the error logger can throttle the system,
preventing further useful work.
For this reason, the system counts certain types of correctable errors and disables reporting if
errors occur too frequently. Error correction remains enabled but calls to the error handler are
disabled. This allows the system to continue running, despite a persistent correctable failure.
The BIOS adds an entry to the event log to indicate that logging for that type of error has been
disabled. This entry indicates a serious hardware problem that must be repaired at the earliest
possible time.
errors occur too frequently. Error correction remains enabled but calls to the error handler are
disabled. This allows the system to continue running, despite a persistent correctable failure.
The BIOS adds an entry to the event log to indicate that logging for that type of error has been
disabled. This entry indicates a serious hardware problem that must be repaired at the earliest
possible time.
The system BIOS implements this feature for correctable bus errors. If ten errors occur within an
hour, the corresponding error handler disables further reporting of that type of error. The BIOS
re-enables logging and SMIs the next time the system is rebooted.
hour, the corresponding error handler disables further reporting of that type of error. The BIOS
re-enables logging and SMIs the next time the system is rebooted.