Intel SE7501WV2 User Manual
BIOS
Intel® Server Board SE7501WV2 TPS
Revision
1.0
Intel reference number C25653-001
132
6.46 Hyper-Threading Technology
Refer to the Intel® Netburst
TM
Micro-architecture BIOS Writer’s Guide for details regarding the
implementation of Hyper-Threading Technology-enabled processors. In addition to these
requirements, the following are also implemented:
requirements, the following are also implemented:
•
Display of processors during POST. BIOS displays the number of physical processors
detected.
detected.
•
Display of processors during BIOS Setup. BIOS displays the corresponding physical
processors.
processors.
•
Number of processors in the MPS table. BIOS only presents the primary thread
processor in the MPS table.
processor in the MPS table.
•
SMBIOS Type 4 structures. Unaffected. Type 4 structures refer to sockets not
processors.
processors.
6.47 OEM Customization
System OEMs can differentiate their products by customizing the BIOS. The extent of
customization is limited to that which is stated in this section.
customization is limited to that which is stated in this section.
The user binary capability of the system BIOS allows system vendors to change the look and feel
of the BIOS and to manage OEM-specific hardware by executing custom code during POST.
Custom code should not hook critical interrupts, reprogram the chip set, or take any other action
that affects the correct functioning of system BIOS.
of the BIOS and to manage OEM-specific hardware by executing custom code during POST.
Custom code should not hook critical interrupts, reprogram the chip set, or take any other action
that affects the correct functioning of system BIOS.
6.48 User Binary
System customers can supply 16 KB of code and data for use during POST and at run-time.
Individual platforms may support a larger user binary. User binary code is executed at several
defined hook points within the POST.
Individual platforms may support a larger user binary. User binary code is executed at several
defined hook points within the POST.
The user binary code is stored in the system flash. If no run-time code is added, the BIOS
temporarily allocates a code buffer according to the POST Memory Manager Specification. If
run-time code is present, the BIOS shadows the entire block as though it were an option ROM.
The BIOS leaves this region writeable to allow the user binary to update any data structures it
defines. System software can locate a run-time user binary by searching for it like an option
ROM, checking each 2KB boundary from C0000h to EFFFFh. The system vendor can place a
signature within the user binary to distinguish it from other option ROMs.
temporarily allocates a code buffer according to the POST Memory Manager Specification. If
run-time code is present, the BIOS shadows the entire block as though it were an option ROM.
The BIOS leaves this region writeable to allow the user binary to update any data structures it
defines. System software can locate a run-time user binary by searching for it like an option
ROM, checking each 2KB boundary from C0000h to EFFFFh. The system vendor can place a
signature within the user binary to distinguish it from other option ROMs.
Intel will provide the tools and reference code to help OEM’s build a user binary. The user
binary must adhere to the following requirements:
binary must adhere to the following requirements:
•
In order to be recognized by the BIOS and protected from runtime memory managers,
the user binary must have an option ROM header (55AA, size).
the user binary must have an option ROM header (55AA, size).
•
The system BIOS performs a scan of the user binary area at predefined points during
POST. Mask bits must be set within the user binary to inform the BIOS if an entry point
exists for a given time during POST.
POST. Mask bits must be set within the user binary to inform the BIOS if an entry point
exists for a given time during POST.
•
The system state must be preserved by the user binary.