Intel SE7501WV2 User Manual

For PC-compatible mode, the ICH3-S provides two 82C59-compatible interrupt controllers.

The 

two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary 
interrupt controller (standard PC configuration).

A single interrupt signal is presented to the 

processors, to which only one processor will respond for servicing. 

The following table recommends the logical interrupt mapping of interrupt sources on the 
SE7501WV2 server board.

The actual interrupt map is defined using configuration registers in the 

ICH3-S. 

INTR Processor 

interrupt. 

NMI 

NMI to processor. 

IRQ1 Keyboard 

interrupt. 

IRQ3 

Serial port A or B interrupt from SIO device, user-configurable. 

IRQ4 

Serial port A or B interrupt from SIO device, user-configurable. 

IRQ5  
IRQ6 Floppy 

disk. 

IRQ7  
IRQ8_L 

Active low RTC interrupt. 

IRQ9  
IRQ10  
IRQ11  
IRQ12 Mouse 

interrupt. 

IRQ14 

Compatibility IDE interrupt from primary channel IDE devices 0 and 1. 

IRQ15  
SMI* 

System Management Interrupt. General purpose indicator sourced by the ICH3-S and BMC to the 
processors. 

SCI* 

System Control Interrupt. Used by system to change sleep states and other system level type 
functions. 

 

The SE7501WV2 server board supports a serialized interrupt delivery mechanism. Serialized 
IRQs (SERIRQ) consist of a start frame, a minimum of 17 IRQ / data channels, and a stop 
frame. Any slave device in the quiet mode may initiate the start frame. While in the continuous 
mode, the start frame is initiated by the host controller. 

For APIC mode, the SE7501WV2 server board interrupt architecture incorporates three Intel

®

 

APIC devices to manage and broadcast interrupts to local APICs in each processor. One of the 
APICs is located in the ICH3-S and the other two APICs are in the P64H2 (one for each PCI