Intel SE7501WV2 User Manual
Intel® Server Board SE7501WV2 TPS
BIOS
Revision 1.0
Intel reference number C25653-001
73
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Intel
®
Xeon™ running at 533MHz Front Side Bus only supports DDR266 DIMMs.
Running these processors with DDR200 DIMMs is an unsupported configuration.
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When Front Side Bus (FSB) is running at 400MHz, DDR266 DIMMs will be run at
200MHz (see Section 3.2 of the BIOS EPS for FSB speed details).
200MHz (see Section 3.2 of the BIOS EPS for FSB speed details).
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When FSB is running at 533MHz, DDR200 DIMMs will result in a BIOS error beep code.
(see section of the BIOS EPS for FSB speed details)
(see section of the BIOS EPS for FSB speed details)
All DIMMs must use SPD EEPROM to be recognized by the BIOS. Mixing vendors of DIMMs is
supported but it is not recommended because the system defaults to the slowest speed that will
work with all of the vendors’ DIMMs.
supported but it is not recommended because the system defaults to the slowest speed that will
work with all of the vendors’ DIMMs.
6.3.1 Memory
Configuration
The SE7501WV2 server board uses the Intel E7501 chipset to configure the system baseboard
memory.
memory.
The SE7501WV2 server BIOS is responsible for configuring and testing the system memory.
The configuration of the system memory involves probing the memory modules for their
characteristics and programming the chipset for optimum performance.
The configuration of the system memory involves probing the memory modules for their
characteristics and programming the chipset for optimum performance.
When the system comes out of reset, the main memory is not usable. The BIOS verifies that the
memory subsystem is functional. It has knowledge of the memory subsystem and it knows the
type of memory, the number of DIMM sites, and their locations.
memory subsystem is functional. It has knowledge of the memory subsystem and it knows the
type of memory, the number of DIMM sites, and their locations.
6.3.2
Memory Sizing and Initialization
During POST, the BIOS tests and sizes memory, and configures the memory controller. The
BIOS determines the operational mode of the MCH based on the number of DIMMS installed
and the type, size, speed, and memory attributes found on the on-board EEPROM or serial
presence detect (SPD) of each DIMM.
BIOS determines the operational mode of the MCH based on the number of DIMMS installed
and the type, size, speed, and memory attributes found on the on-board EEPROM or serial
presence detect (SPD) of each DIMM.
The memory system is based on rows. Since the SE7501WV2 server board supports a 2-way
interleave, DIMMs must be populated in pairs. This means two DIMMs are required to constitute
a row. Although DIMMs within a row must be identical, the BIOS supports various DIMM sizes
and configurations allowing the rows of memory to be different. Memory sizing and configuration
is guaranteed only for DIMMs listed on the Intel tested memory list. Intel only tests identical
DIMMs in the SE7501WV2 server board.
interleave, DIMMs must be populated in pairs. This means two DIMMs are required to constitute
a row. Although DIMMs within a row must be identical, the BIOS supports various DIMM sizes
and configurations allowing the rows of memory to be different. Memory sizing and configuration
is guaranteed only for DIMMs listed on the Intel tested memory list. Intel only tests identical
DIMMs in the SE7501WV2 server board.
The memory-sizing algorithm determines the size of each row of DIMMs. The BIOS tests
extended memory according to the option selected in the BIOS Setup Utility. The total amount
of configured memory can be found using INT 15h, AH = 88h; INT 15h, function E801h, or INT
15h, function E820h.
extended memory according to the option selected in the BIOS Setup Utility. The total amount
of configured memory can be found using INT 15h, AH = 88h; INT 15h, function E801h, or INT
15h, function E820h.
Because the system supports up to 12 GB of memory, the BIOS creates a hole just below 4 GB
to accommodate the system BIOS flash, APIC memory, and memory-mapped I/O located on
32-bit PCI devices. The size of this hole depends upon the number of PCI cards and the
memory mapped resources requested by them. It is typically less than 128 MB.
to accommodate the system BIOS flash, APIC memory, and memory-mapped I/O located on
32-bit PCI devices. The size of this hole depends upon the number of PCI cards and the
memory mapped resources requested by them. It is typically less than 128 MB.