Mitsubishi Electronics FX3G User Manual
105
FX
3S
/FX
3G
/FX
3GC
/FX
3U
/FX
3UC
Series
Programming Manual - Basic & Applied Instruction Edition
4 Devices in Detail
4.6 Counter [C]
1
Introdu
ction
2
Ov
ervi
ew
ew
3
Instruction
Li
st
4
D
evices
in Det
ai
l
5
Specifi
ed the
De
vice
&
C
onst
ant
ant
6
Bef
ore
ore
Pr
og
ra
mmi
ng
ng
7
Bas
ic
ic
Instruction
8
FN
C00-FN
C00-FN
C0
9
Program Fl
ow
9
FNC
10-FN
C19
Mov
e & Com
e & Com
pare
10
FNC
20-FNC
29
Arith. & Lo
gi
c
Operati
on
2. 32-bit counter
1) Specification by constant (K)
2) Indirect specification (D)
4.6.6
Response speed of counters
Counters execute counting by cyclic operating for contact operations of internal signals X, Y, M, S, C, etc. inside the
PLC.
For example, when X011 is specified as counting input, its ON duration and OFF duration should be longer than the
scan time of the PLC (which is tens of Hz or less usually).
On the other hand, high-speed counters described later execute counting as an interrupt processing for specific input,
and can execute counting at 5 k to 6 kHz regardless of the scan time.
PLC.
For example, when X011 is specified as counting input, its ON duration and OFF duration should be longer than the
scan time of the PLC (which is tens of Hz or less usually).
On the other hand, high-speed counters described later execute counting as an interrupt processing for specific input,
and can execute counting at 5 k to 6 kHz regardless of the scan time.
→ For high-speed counters, refer to Section 4.7 or 4.8.
4.6.7
Handling counters as numeric devices
Counters use output contacts operating in accordance with the set value or use the counter value (current value) as
numeric data for control.
The figure below shows the structure of the current value register of a counter. When a counter number is specified in
an operand of an applied instruction in execution, the counter is handled as a device storing 16-bit or 32-bit data in the
same way as data register.
A 32-bit counter is handled as 32-bit data.
numeric data for control.
The figure below shows the structure of the current value register of a counter. When a counter number is specified in
an operand of an applied instruction in execution, the counter is handled as a device storing 16-bit or 32-bit data in the
same way as data register.
A 32-bit counter is handled as 32-bit data.
1. Structure of register storing current value of counter
1) 16-bit
2) 32-bit
X003
C200
K43,210
Constant (decimal constant):
−2,147,483,648 to +2,147,483,647
43210 counts
X001
FNC 12
DMOV
K43210 D5(D6)
X003
C200
D5(D6)
Pairs of data registers are used for indirect specification.
Use a 32-bit instruction for writing the set value, and make
sure that the latter of paired registers (D6 in this example)
does not overlap with other programs because it is not
shown in ladder format.
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
b15
Sign
0: Positive
0: Positive
number
1: Negative
number
*1
b0
High
order
Low
order
16 bits
Available numeric value range
16-bit counter: 0 to 32767
32-bit counter:
−2,147,483,648 to
+2,147,483,647
*1. The sign is valid only when a counter is handled as a substitute for data register.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
1
6384
b31
Sign
0: Positive
0: Positive
number
1: Negative
number
b0
High
order
Low
order
32 bits
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
3
2768
6
5536
131
,072
262
,144
524
,288
1,048
,576
2,097
,152
4,194
,304
8,388
,608
16,77
7,216
33,55
4,432
67,10
8,864
134,21
7,728
268,43
5,456
536,87
0,912
1,073,74
1,824