Renesas R5S72623 User Manual

 

 

 

 

 

Section 9   Bus State Controller 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 245 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

18 to 16 

IWRRS[2:0]  011 

R/W 

Idle Cycles for Read-Read in the Same Space 

Specify the number of idle cycles to be inserted after 
the access to a memory that is connected to the 
space. The target cycle is a read-read cycle of which 
continuous access cycles are for the same space.  

000: No idle cycle inserted 

001: 1 idle cycle inserted 

010: 2 idle cycles inserted 

011: 4 idle cycles inserted 

100: 6 idle cycles inserted 

101: 8 idle cycles inserted 

110: 10 idle cycles inserted 

111: 12 idle cycles inserted 

15 

 0 

R 

Reserved 

This bit is always read as 0. The write value should 
always be 0. 

14 to 12 

TYPE[2:0] 

000 

R/W 

Specify the type of memory connected to a space. 

000: Normal space 

001: Burst ROM (clock asynchronous) 

010: MPX-I/O 

011: SRAM with byte selection 

100: SDRAM 

101: PCMCIA 

110: Reserved (setting prohibited) 

111: Burst ROM (clock synchronous) 

For details for memory type in each area, see table 
9.2. 

Note:  When connecting the burst ROM to the CS0 

space in boot mode 0, change the CS0WCR 
register to the settings by the burst ROM 
CS0WCR uses and then set TYPE[2:0] to the 
burst ROM setting. In boot mode 2 and 3, 
memory access should be performed after 
setting CS0BCR and CS0WCR.