Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Datasheet
107
DRAM Controller Registers (D0:F0)
5.2.10
C0CYCTRKWR—Channel 0 CYCTRK WR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 256–257h
Default Value:
0000h
Access:
RW
Size:
16 bits
Channel 0 CYCTRK WR registers.
Bit
Access
Default
Value
Description
15:12
RW
0h
ACT To Write Delay (C0sd_cr_act_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the
same rank-bank. This field corresponds to t
allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the
same rank-bank. This field corresponds to t
RCD_wr
in the DDR Specificaiton.
11:8
RW
0h
Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
indicates the minimum allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
7:4
RW
0h
Different Rank Write to Write Delay (C0sd_cr_wrdr_wr): This field
register indicates the minimum allowed spacing (in DRAM clocks) between two
WRITE commands to different ranks. This field corresponds to t
register indicates the minimum allowed spacing (in DRAM clocks) between two
WRITE commands to different ranks. This field corresponds to t
WR_WR
in the
DDR Specification.
3:0
RW
0h
READ To WRTE Delay (C0sd_cr_rd_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between the READ and WRITE commands.
This field corresponds to t
allowed spacing (in DRAM clocks) between the READ and WRITE commands.
This field corresponds to t
RD_WR
.