Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
114
Datasheet
5.2.18
C1DRB1—Channel 1 DRAM Rank Boundary Address 1
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 602–603h
Default Value:
0000h
Access:
RO, RW/L
Size:
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
5.2.19
C1DRB2—Channel 1 DRAM Rank Boundary Address 2
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 604–605h
Default Value:
0000h
Access:
RW/L, RO
Size:
16 bits
The operation of this register is detailed in the description for C0DRB0 register.
Bit
Access
Default
Value
Description
15:10
RO
000000b Reserved
9:0
RW/L
000h
Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1): See C0DRB1
register.
In stacked mode, if this is the topmost populated rank in Channel 1, program
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
register.
In stacked mode, if this is the topmost populated rank in Channel 1, program
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
Bit
Access
Default
Value
Description
15:10
RO
000000b Reserved
9:0
RW/L
000h
Channel 1 DRAM Rank Boundary Address 2 (C1DRBA2): See C0DRB2
register.
In stacked mode, if this is the topmost populated rank in Channel 1, program
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
register.
In stacked mode, if this is the topmost populated rank in Channel 1, program
this value to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.