Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
120
Datasheet
5.2.28
C1REFRCTRL—Channel 1 DRAM Refresh Control
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 669–66Eh
Default Value:
021830000C30h
Access:
RW, RO
Size:
48 bits
This register provides the settings to configure the DRAM refresh controller.
Bit
Access
Default
Value
Description
47:42
RO
00h
Reserved
41:37
RW
10000b
Direct Rcomp Quiet Window (DIRQUIET): This configuration setting
indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
36:32
RW
11000b
Indirect Rcomp Quiet Window (INDIRQUIET): This configuration setting
indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
indicates the amount of refresh_tick events to wait before the service of rcomp
request in non-default mode of independent rank refresh.
31:27
RW
00110b
Rcomp Wait (RCOMPWAIT): This configuration setting indicates the amount
of refresh_tick events to wait before the service of rcomp request in non-default
mode of independent rank refresh.
of refresh_tick events to wait before the service of rcomp request in non-default
mode of independent rank refresh.
26
RO
0b
Reserved
25
RW
0b
Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh
counter to count during times that DRAM is not in self-refresh, but refreshes are
not enabled. Such a condition may occur due to need to reprogram DIMMs
following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is no mode where
Refresh is enabled but the counter does not run) So, in conjunction with bit 23
REFEN, the modes are:
[REFEN:REFCNTEN]Description
counter to count during times that DRAM is not in self-refresh, but refreshes are
not enabled. Such a condition may occur due to need to reprogram DIMMs
following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is no mode where
Refresh is enabled but the counter does not run) So, in conjunction with bit 23
REFEN, the modes are:
[REFEN:REFCNTEN]Description
[0:0]
Normal refresh disable
[0:1]
Refresh disabled, but counter is accumulating refreshes.
[1:X]
Normal refresh enable
24
RW
0b
All Rank Refresh (ALLRKREF): This configuration bit enables (by default) that
all the ranks are refreshed in a staggered/atomic fashion. If set, the ranks are
refreshed in an independent fashion.
all the ranks are refreshed in a staggered/atomic fashion. If set, the ranks are
refreshed in an independent fashion.
23
RW
0b
Refresh Enable (REFEN): Refresh is enabled.
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
22
RW
0b
DDR Initialization Done (INITDONE): Indicates that DDR initialization is
complete.
complete.
21:20
RO
00b
Reserved
19:18
RW
00b
DRAM Refresh Panic Watermark (REFPANICWM): When the refresh count
exceeds this level, a refresh request is launched to the scheduler and the
dref_panic flag is set.
00 = 5
01 = 6
10 = 7
11 = 8
exceeds this level, a refresh request is launched to the scheduler and the
dref_panic flag is set.
00 = 5
01 = 6
10 = 7
11 = 8