Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Datasheet
129
DRAM Controller Registers (D0:F0)
5.2.43
EPDREFCONFIG—EP DRAM Refresh Configuration
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: A30–A33h
Default Value:
40000C30h
Access:
RW, RO
Size:
32 bits
This register provides the settings to configure the EPD refresh controller.
0
RW
0b
Indicates Only 1 Rank Enabled (sd0_cr_singledimmpop): This field
indicates the that only 1 rank is enabled. This bit needs to be set if there is one
active rank and no odt ranks, or if there is one active rank and one ODT rank and
they are the same rank.
indicates the that only 1 rank is enabled. This bit needs to be set if there is one
active rank and no odt ranks, or if there is one active rank and one ODT rank and
they are the same rank.
Bit
Access
Default
Value
Description
Bit
Access
Default
Value
Description
31
RO
0b
Reserved
30:29
RW
10b
EPDunit refresh count addition for self refresh exit. (EPDREF4SR):
Configuration indicating the number of additional refreshes that needs to be
added to the refresh request count after exiting self refresh.
Typical value is to add 2 refreshes.
00 = Add 0 Refreshes
01 = Add 1 Refreshes
10 = Add 2 Refreshes
11 = Add 3 Refreshes
Configuration indicating the number of additional refreshes that needs to be
added to the refresh request count after exiting self refresh.
Typical value is to add 2 refreshes.
00 = Add 0 Refreshes
01 = Add 1 Refreshes
10 = Add 2 Refreshes
11 = Add 3 Refreshes
28
RW
0b
Refresh Counter Enable (REFCNTEN): This bit is used to enable the refresh
counter to count during times that DRAM is not in self-refresh, but refreshes are
not enabled. Such a condition may occur due to need to reprogram DIMMs
following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is no mode where
Refresh is enabled but the counter does not run) So, in conjunction with bit [23]
REFEN, the modes are:
[REFEN:REFCNTEN] Description
counter to count during times that DRAM is not in self-refresh, but refreshes are
not enabled. Such a condition may occur due to need to reprogram DIMMs
following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is no mode where
Refresh is enabled but the counter does not run) So, in conjunction with bit [23]
REFEN, the modes are:
[REFEN:REFCNTEN] Description
[0:0]
Normal refresh disable
[0:1]
Refresh disabled, but counter is accumulating refreshes.
[1:X]
Normal refresh enable
27
RW
0b
Refresh Enable (REFEN): Refresh is enabled.
0 = Disabled
1 = Enabled
0 = Disabled
1 = Enabled
26
RW
0b
DDR Initialization Done (INITDONE): Indicates that DDR initialization is
complete.
complete.
25:22
RW
0000b
DRAM Refresh Hysterisis (REFHYSTERISIS): Hysterisis level - Useful for
dref_high watermark cases. The dref_high flag is set when the dref_high
watermark level is exceeded, and is cleared when the refresh count is less than
the hysterisis level. This bit should be set to a value less than the high
watermark level.
0000 = 0
0001 = 1
.......
1000 = 8
dref_high watermark cases. The dref_high flag is set when the dref_high
watermark level is exceeded, and is cleared when the refresh count is less than
the hysterisis level. This bit should be set to a value less than the high
watermark level.
0000 = 0
0001 = 1
.......
1000 = 8