Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

137

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: CE4h

Default Value:

00h

Access:

RW/L, RO, RW/L/K 

Size:

8 bits

All bits in this register are reset to their defaults by PLTRST#.

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: CEA–CEBh

Default Value:

0000h

Access:

RO, RWC 

Size:

16 bits

This register is used to report which specific error condition resulted in the Device 0 

Function 0 ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR 

Thermal Event. SW can examine the current state of the thermal zones by examining 

the TSS. Software can distinguish internal or external Trip Event by examining 

EXTTSCS.

Software must write a 1 to clear the status bits in this register.

Following scenario is possible. An interrupt is initiated on a rising temperature trip, the 

appropriate DMI cycles are generated, and eventually the software services the 

interrupt and sees a rising temperature trip as the cause in the status bits for the 

interrupts. Assume that the software then goes and clears the local interrupt status bit 

in the TIS register for that trip event. It is possible at this point that a falling 

temperature trip event occurs before the software has had the time to clear the global 

interrupts status bit. But since software has already looked at the status register before 

this event happened, software may not clear the local status flag for this event. 

Therefore, after the global interrupt is cleared by sw, sw must look at the 

instantaneous status in the TSS register. 

All bits in this register are reset to their defaults by PLTRST#.

7:4

RO

0b

Reserved 

3

RW/L

0b

Halt on Catastrophic (HOC): 
0 = Continue to toggle clocks when the catastrophic sensor trips.
1 = All clocks are disabled when the catastrophic sensor trips. A system reset is 

required to bring the system out of a halt from the thermal sensor.

2:1

RO

00b

Reserved 

0

RW/L/K

0b

Hardware Throttling Lock Bit (HTL): This bit locks bits [7:0] of this register. 
The register bits are unlocked.
1 = The register bits are locked. It may only be set to a 0 by a hardware reset. 
Writing a 0 to this bit has no effect.