Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

151

8

RW

0b

SERR# Message Enable (SERRE1): Controls Device 1 SERR# messaging. The 
MCH communicates the SERR# condition by sending an SERR message to the 
ICH. This bit, when set, enables reporting of non-fatal and fatal errors detected 
by the device to the Root Complex. Note that errors are reported if enabled 
either through this bit or through the PCI-Express specific bits in the Device 
Control Register.
0 = The SERR message is generated by the MCH for Device 1 only under 

conditions enabled individually through the Device Control Register.

1 = The MCH is enabled to generate SERR messages which will be sent to the 

ICH for specific Device 1 error conditions generated/detected on the primary 
side of the virtual PCI to PCI bridge (not those received by the secondary 
side). The status of SERRs generated is reported in the PCISTS1 register.

7

RO

0b

Reserved 

6

RW

0b

Parity Error Response Enable (PERRE): Controls whether or not the Master 
Data Parity Error bit in the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN be set.

5:3

RO

0b

Reserved 

2

RW

0b

Bus Master Enable (BME): Controls the ability of the PCI Express port to 
forward Memory and IO Read/Write Requests in the upstream direction.
0 = This device is prevented from making memory or IO requests to its primary 

bus. Note that according to PCI Specification, as MSI interrupt messages are 
in-band memory writes, disabling the bus master enable bit prevents this 
device from generating MSI interrupt messages or passing them from its 
secondary bus to its primary bus. Upstream memory writes/reads, IO 
writes/reads, peer writes/reads, and MSIs will all be treated as illegal cycles. 
Writes are forwarded to memory address C0000h with byte enables de-
asserted. Reads will be forwarded to memory address C0000h and will 
return Unsupported Request status (or Master abort) in its completion 
packet.

1 = This device is allowed to issue requests to its primary bus. Completions for 

previously issued memory read requests on the primary bus will be issued 
when the data is available.

 This bit does not affect forwarding of Completions from the primary interface to 
the secondary interface.

1

RW

0b

Memory Access Enable (MAE): 
0 = All of device 1's memory space is disabled.
1 = Enable the Memory and Pre-fetchable memory address ranges defined in the 

MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.

0

RW

0b

I/O Access Enable (IOAE): 
0 = All of device 1's I/O space is disabled.
1 = Enable the I/O address range defined in the IOBASE1, and IOLIMIT1 

registers.