Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

163

B/D/F/Type:

0/1/0/PCI

Address Offset: 2C–2Fh

Default Value:

00000000h

Access:

RW 

Size:

32 bits

The functionality associated with this register is present in the PCI Express design 

implementation.

This register in conjunction with the corresponding Upper Limit Address register 

controls the processor to PCI Express prefetchable memory access routing based on 

the following formula:

PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits 

A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register 

are read/write and correspond to address bits A[39:32] of the 40-bit address. This 

register must be initialized by the configuration software. For the purpose of address 

decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined 

memory address range will be at the top of a 1MB aligned memory block. 

Note that prefetchable memory range is supported to allow segregation by the 

configuration software between the memory ranges that must be defined as UC and the 

ones that can be designated as a USWC (i.e. prefetchable) from the processor 

perspective.

B/D/F/Type:

0/1/0/PCI

Address Offset: 34h

Default Value:

88h

Access:

RO 

Size:

8 bits

The capabilities pointer provides the address offset to the location of the first entry in 

this device's linked list of capabilities.

31:0

RW

0000000

0h

Prefetchable Memory Address Limit (MLIMITU): This field corresponds to 
A[63:32] of the upper limit of the prefetchable Memory range that will be passed 
to PCI Express. 

7:0

RO

88h

First Capability (CAPPTR1): The first capability in the list is the Subsystem ID 
and Subsystem Vendor ID Capability.