Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Datasheet
167
Host-Primary PCI Express* Bridge Registers (D1:F0)
6.26
PM_CS1—Power Management Control/Status
B/D/F/Type:
0/1/0/PCI
Address Offset: 84–87h
Default Value:
00000008h
Access:
RO, RW, RW/P
Size:
32 bits
Bit
Access
Default
Value
Description
31:16
RO
0000h
Reserved
15
RO
0b
PME Status (PMESTS): This bit indicates that this device does not support
PMEB generation from D3cold.
PMEB generation from D3cold.
14:13
RO
00b
Data Scale (DSCALE): This field indicates that this device does not support the
power management data register.
power management data register.
12:9
RO
0h
Data Select (DSEL): This field indicates that this device does not support the
power management data register.
power management data register.
8
RW/P
0b
PME Enable (PMEE): This bit indicates that this device does not generate PMEB
assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
7:2
RO
0000b
Reserved
1:0
RW
00b
Power State (PS): This field indicates the current power state of this device
and can be used to set the device into a new power state. If software attempts
to write an unsupported state to this field, write operation must complete
normally on the bus, but the data is discarded and no state change occurs.
00 = D0
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The device
must return to the D0 state in order to be fully-functional.
When the Power State is other than D0, the bridge will Master Abort (i.e. not
claim) any downstream cycles (with exception of type 0 configuration cycles).
Consequently, these unclaimed cycles will go down DMI and come back up as
Unsupported Requests, which the MCH logs as Master Aborts in Device 0
PCISTS[13]
There is no additional hardware functionality required to support these Power
States.
and can be used to set the device into a new power state. If software attempts
to write an unsupported state to this field, write operation must complete
normally on the bus, but the data is discarded and no state change occurs.
00 = D0
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The device
must return to the D0 state in order to be fully-functional.
When the Power State is other than D0, the bridge will Master Abort (i.e. not
claim) any downstream cycles (with exception of type 0 configuration cycles).
Consequently, these unclaimed cycles will go down DMI and come back up as
Unsupported Requests, which the MCH logs as Master Aborts in Device 0
PCISTS[13]
There is no additional hardware functionality required to support these Power
States.