Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

184

Datasheet

B/D/F/Type:

0/1/0/PCI

Address Offset: C0–C3h

Default Value:

00000000h

Access:

RO, RWC 

Size:

32 bits

This register provides information about PCI Express Root Complex specific 

parameters.

B/D/F/Type:

0/1/0/PCI

Address Offset: EC–EFh

Default Value:

00000000h

Access:

RO, RW 

Size:

32 bits

This register controls functionality that is needed by Legacy (non-PCI Express aware) 

OSs during run time.

31:18

RO

0000h

Reserved

17

RO

0b

PME Pending (PMEP): Indicates that another PME is pending when the PME 
Status bit is set. When the PME Status bit is cleared by software; the PME is 
delivered by hardware by setting the PME Status bit again and updating the 
Requestor ID appropriately. The PME pending bit is cleared by hardware if no 
more PMEs are pending.

16

RWC

0b

PME Status (PMES): Indicates that PME was asserted by the requestor ID 
indicated in the PME Requestor ID field. Subsequent PMEs are kept pending until 
the status register is cleared by writing a 1 to this field.

15:0

RO

0000h

PME Requestor ID (PMERID): Indicates the PCI requestor ID of the last PME 
requestor.

31:3

RO

0000000

0h

Reserved

2

RW

0b

PME GPE Enable (PMEGPE): 
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received (Assert_PMEGPE and 

Deassert_PMEGPE messages on DMI). This enables the MCH to support 
PMEs on the PCI Express port under legacy OSs.

1

RO

0b

Reserved 

0

RW

0b

General Message GPE Enable (GENGPE): 
0 = Do not forward received GPE assert/de-assert messages.
1 = Forward received GPE assert/de-assert messages. These general GPE 

message can be received via the PCI Express port from an external Intel 
device and will be subsequently forwarded to the ICH (via Assert_GPE and 
Deassert_GPE messages on DMI).