Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

189

B/D/F/Type:

0/1/0/MMR

Address Offset: 11A–11Bh

Default Value:

0002h

Access:

RO

Size:

16 bits

This register reports the Virtual Channel specific status.

B/D/F/Type:

0/1/0/MMR

Address Offset: 140–143h

Default Value:

00010005h

Access:

RO 

Size:

32 bits

This capability declares links from this element (PCI Express) to other elements of the 

root complex component to which it belongs. See PCI Express specification for link/

topology declaration requirements.

15:2

RO

0000h

Reserved 

1

RO

1b

VC0 Negotiation Pending (VC0NP): 
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or 

disabling).

This bit indicates the status of the process of Flow Control initialization. It is set 
by default on Reset, as well as whenever the corresponding Virtual Channel is 
Disabled or the Link is in the DL_Down state. It is cleared when the link 
successfully exits the FC_INIT2 state.
Before using a Virtual Channel, software must check whether the VC Negotiation 
Pending fields for that Virtual Channel are cleared in both Components on a Link.

0

RO

0b

Reserved

31:20

RO

000h

Pointer to Next Capability (PNC): This is the last capability in the PCI Express 
extended capabilities list.

19:16

RO

1h

Link Declaration Capability Version (LDCV): Hardwired to 1 to indicate 
compliances with the 1.1 version of the PCI Express specification.

15:0

RO

0005h

Extended Capability ID (ECID): Value of 0005h identifies this linked list item 
(capability structure) as being for PCI Express Link Declaration Capability.