Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
242
Datasheet
8.39
LCTL—Link Control
B/D/F/Type:
0/6/0/PCI
Address Offset: B0–B1h
Default Value:
0000h
Access:
RO, RW, RW/SC
Size:
16 bits
This register allows control of PCI Express link.
Bit
Access
Default
Value
Description
15:12
RO
0000000b Reserved
11
RW
0b
Link Autonomous Bandwidth Interrupt Enable: When Set, this bit enables
the generation of an interrupt to indicate that the Link Autonomous Bandwidth
Status bit has been set.
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
the generation of an interrupt to indicate that the Link Autonomous Bandwidth
Status bit has been set.
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability must
hardwire this bit to 0b.
10
RW
0b
Link Bandwidth Management Interrupt Enable: When Set, this bit enables
the generation of an interrupt to indicate that the Link Bandwidth Management
Status bit has been set.
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
the generation of an interrupt to indicate that the Link Bandwidth Management
Status bit has been set.
This bit is not applicable and is reserved for Endpoint devices, PCI Express to
PCI/PCI-X bridges, and Upstream Ports of Switches.
9
R0
0b
Hardware Autonomous Width Disable: When Set, this bit disables
hardware from changing the Link width for reasons other than attempting to
correct unreliable Link operation by reducing Link width.
Devices that do not implement the ability autonomously to change Link width
are permitted to hardwire this bit to 0b.
The MCH does not support autonomous width change. So, this bit is "RO".
hardware from changing the Link width for reasons other than attempting to
correct unreliable Link operation by reducing Link width.
Devices that do not implement the ability autonomously to change Link width
are permitted to hardwire this bit to 0b.
The MCH does not support autonomous width change. So, this bit is "RO".
8
RO
0b
Enable Clock Power Management (ECPM): Applicable only for form factors
that support a "Clock Request" (CLKREQ#) mechanism, this enable functions
as follows:
0 = Clock power management is disabled and device must hold CLKREQ#
that support a "Clock Request" (CLKREQ#) mechanism, this enable functions
as follows:
0 = Clock power management is disabled and device must hold CLKREQ#
signal low
1 = The device is permitted to use CLKREQ# signal to power manage link clock
according to protocol defined in appropriate form factor specification.
Default value of this field is 0b.
Components that do not support Clock Power Management (as indicated by a
0b value in the Clock Power Management bit of the Link Capabilities Register)
must hardwire this bit to 0b.
Components that do not support Clock Power Management (as indicated by a
0b value in the Clock Power Management bit of the Link Capabilities Register)
must hardwire this bit to 0b.
7
RW
0b
Extended Synch (ES):
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting the L0s
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when exiting the L0s
state and when in the Recovery state.
This mode provides external devices (e.g., logic analyzers) monitoring the Link
time to achieve bit and symbol lock before the link enters L0 and resumes
communication.
This is a test mode only and may cause other undesired side effects such as
buffer overflows or underruns.
time to achieve bit and symbol lock before the link enters L0 and resumes
communication.
This is a test mode only and may cause other undesired side effects such as
buffer overflows or underruns.