Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

251

B/D/F/Type:

0/6/0/MMR

Address Offset: 100–103h

Default Value:

14010002h

Access:

RO 

Size:

32 bits

This register indicates PCI Express device Virtual Channel capabilities. Extended 

capability structures for PCI Express devices are located in PCI Express extended 

configuration space and have different field definitions than standard PCI capability 

structures.

B/D/F/Type:

0/6/0/MMR

Address Offset: 104–107h

Default Value:

00000000h

Access:

RO 

Size:

32 bits

This register describes the configuration of PCI Express Virtual Channels associated 

with this port.

31:20

RO

140h

Pointer to Next Capability (PNC): The Link Declaration Capability is the next 
in the PCI Express extended capabilities list.

19:16

RO

1h

PCI Express Virtual Channel Capability Version (PCIEVCCV): Hardwired to 
1 to indicate compliances with the 1.1 version of the PCI Express specification.

15:0

RO

0002h

Extended Capability ID (ECID): Value of 0002h identifies this linked list item 
(capability structure) as being for PCI Express Virtual Channel registers.

31:7

RO

00000h Reserved 

6:4

RO

000b

Low Priority Extended VC Count (LPEVCC): This field indicates the number 
of (extended) Virtual Channels in addition to the default VC belonging to the low-
priority VC (LPVC) group that has the lowest priority with respect to other VC 
resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.

3

RO

0b

Reserved

2:0

RO

000b

Extended VC Count (EVCC): This field indicates the number of (extended) 
Virtual Channels in addition to the default VC supported by the device.