Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

262

Datasheet

B/D/F/Type:

0/0/0/DMIBAR

Address Offset: 14–17h

Default Value:

800000FFh

Access:

RO, RW 

Size:

32 bits

This register controls the resources associated with PCI Express Virtual Channel 0.

31

RO

1b

Virtual Channel 0 Enable (VC0E): For VC0 this is hardwired to 1 and read 
only as VC0 can never be disabled.

30:27

RO

0h

Reserved 

26:24

RO

000b

Virtual Channel 0 ID (VC0ID): Assigns a VC ID to the VC resource. For VC0 
this is hardwired to 0 and read only.

23:20

RO

0h

Reserved 

19:17

RW

000b

Port Arbitration Select (PAS): This field configures the VC resource to provide 
a particular Port Arbitration service. Valid value for this field is a number 
corresponding to one of the asserted bits in the Port Arbitration Capability field 
of the VC resource. Because only bit 0 of that field is asserted.
This field will always be programmed to 1.

16:8

RO

000h

Reserved 

7:1

RW

7Fh

Traffic Class / Virtual Channel 0 Map (TCVC0M): This field indicates the TCs 
(Traffic Classes) that are mapped to the VC resource. Bit locations within this 
field correspond to TC values.
For example, when bit 7 is set in this field, TC7 is mapped to this VC resource. 
When more than one bit in this field is set, it indicates that multiple TCs are 
mapped to the VC resource. In order to remove one or more TCs from the TC/VC 
Map of an enabled VC, software must ensure that no new or outstanding 
transactions with the TC labels are targeted at the given Link.

0

RO

1b

Traffic Class 0 / Virtual Channel 0 Map (TC0VC0M): Traffic Class 0 is always 
routed to VC0.