Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

267

The MCH supports Dual-Core Intel

®

 Xeon

®

 Processor 3000 Series and Quad-Core 

Intel

®

 Xeon

®

 Processor 3200 Series processors. The cache line size is 64 bytes. Source 

synchronous transfer is used for the address and data signals. The address signals are 

double pumped and a new address can be generated every other bus clock. At 200/

267/333MHz bus clock the address signals run at 667MT/s. The data is quad pumped 

and an entire 64B cache line can be transferred in two bus clocks. At 200/266/333MHz 

bus clock, the data signals run at 800/1066/1333MT/s for a maximum bandwidth of 

6.4/8.5/10.6GB/s.

The Scalable Bus supports up to 12 simultaneous outstanding transactions. 

The MCH supports only one outstanding deferred transaction on the FSB.

The MCH integrates GTL+ termination resistors on die. 

The MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data 

from the processor. DBI limits the number of data signals that are driven to a low 

voltage on each quad pumped data phase. This decreases the worst-case power 

consumption of the MCH. HDINV[3:0]# indicate if the corresponding 16 bits of data are 

inverted on the bus for each quad pumped data phase: 

When the processor or the MCH drives data, each 16-bit segment is analyzed. If more 

than 8 of the 16 signals would normally be driven low on the bus, the corresponding 

HDINV# signal will be asserted, and the data will be inverted prior to being driven on 

the bus. When the processor or the MCH receives data, it monitors HDINV#[3:0] to 

determine if the corresponding data segment should be inverted.

HDINV0#

HD[15:0]#

HDINV1#

HD[31:16]#

HDINV2#

HD[47:32]#

HDINV3#

HD[63:48]#