Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet

Datasheet

53

The MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express 

bus interface when processor initiated I/O cycle addresses are within the PCI Express I/

O address range. This range is controlled via the I/O Base Address (IOBASE) and I/O 

Limit Address (IOLIMIT) registers in MCH Device 1 configuration space.

Address decoding for this range is based on the following concept. The top 4 bits of the 

respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of an 

I/O address. For the purpose of address decoding, the MCH assumes that lower 12 

address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the I/O 

limit address are FFFh. This forces the I/O address range alignment to 4 KB boundary 

and produces a size granularity of 4 KB.

The MCH positively decodes I/O accesses to PCI Express I/O address space as defined 

by the following equation:

I/O_Base_Address ≤ Processor I/O Cycle Address ≤ I/O_Limit_Address

The effective size of the range is programmed by the plug-and-play configuration 

software and it depends on the size of I/O space claimed by the PCI Express device.

Note that the MCH Device 1 and/or Device 6 I/O address range registers defined above 

are used for all I/O space allocation for any devices requiring such a window on PCI 

Express. 

The PCICMD1 register can disable the routing of I/O cycles to PCI Express.