Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333 Data Sheet
Product codes
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
84
Datasheet
5.1.23
PAM6—Programmable Attribute Map 6
B/D/F/Type:
0/0/0/PCI
Address Offset: 96h
Default Value:
00h
Access:
RO, RW/L
Size:
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h–0EFFFFh.
5.1.24
LAC—Legacy Access Control
B/D/F/Type:
0/0/0/PCI
Address Offset: 97h
Default Value:
00h
Access:
RW/L, RO
Size:
8 bits
This 8-bit register controls a fixed DRAM hole from 15–16 MB.
Bit
Access
Default
Value
Description
7:6
RO
00b
Reserved
5:4
RW/L
00b
0EC000h–0EFFFFh Attribute (HIENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
read and write cycles that address the BIOS area from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
3:2
RO
00b
Reserved
1:0
RW/L
00b
0E8000h–0EBFFFh Attribute (LOENABLE): This field controls the steering of
read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
read and write cycles that address the BIOS area from 0E0000h to 0E3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes are forwarded to
DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
This register is locked by Intel TXT.
Bit
Access
Default
Value
Description
7
RW/L
0b
Hole Enable (HEN): This field enables a memory hole in DRAM space. The
DRAM that lies "behind" this space is not remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
This bit is Intel TXT lockable.
DRAM that lies "behind" this space is not remapped.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
This bit is Intel TXT lockable.
6:0
RO
0s
Reserved