Fujitsu Intel Xeon X3210 S26361-F3476-E321 Data Sheet
Product codes
S26361-F3476-E321
Quad-Core Intel® Xeon® Processor 3200 Series Datasheet
11
Introduction
1
Introduction
The Quad-Core Intel
®
Xeon
®
Processor 3200 Series are the first server quad-core
processors that combine the performance and power efficiencies of four low-power
microarchitecture cores to enable a new level of multi-tasking, multi-media, and
gaming experiences. They are 64-bit processors that maintain compatibility with IA-32
software.
microarchitecture cores to enable a new level of multi-tasking, multi-media, and
gaming experiences. They are 64-bit processors that maintain compatibility with IA-32
software.
The processors use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plug
into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket. The processors are based on 65 nm process technology.
into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket. The processors are based on 65 nm process technology.
Note:
In this document the Quad-Core Intel Xeon Processor 3200 Series are referred to
simply as “processor.”
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2) and
Streaming SIMD Extensions 3 (SSE3). The processor supports several advanced
technologies including Execute Disable Bit, Intel
Streaming SIMD Extensions 3 (SSE3). The processor supports several advanced
technologies including Execute Disable Bit, Intel
®
64 architecture, and Intel
®
Virtualization Technology (VT).
The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol
like the Intel
like the Intel
®
Pentium
®
4 processor. The FSB uses Source-Synchronous Transfer (SST)
of address and data to improve performance by transferring data four times per bus
clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a "double-
clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 8.5 GB/s.
clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a "double-
clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 8.5 GB/s.
The processor uses some of the infrastructure already enabled by the
775_VR_CONFIG_05B platforms including heatsink, heatsink retention mechanism,
and socket. Supported platforms may need to be refreshed to ensure the correct
voltage regulation (VRD11) and PECI support is enabled. Manufacturability is a high
priority; hence, mechanical assembly may be completed from the top of the baseboard
and should not require any special tooling.
775_VR_CONFIG_05B platforms including heatsink, heatsink retention mechanism,
and socket. Supported platforms may need to be refreshed to ensure the correct
voltage regulation (VRD11) and PECI support is enabled. Manufacturability is a high
priority; hence, mechanical assembly may be completed from the top of the baseboard
and should not require any special tooling.
The processor includes an address bus power-down capability that removes power from
the address and data signals when the FSB is not in use. This feature is always enabled
on the processor.
the address and data signals when the FSB is not in use. This feature is always enabled
on the processor.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.