Intel Celeron Mobile 585 LF80537NF0481M User Manual
Product codes
LF80537NF0481M
R
Specification Update
17
V6.
The Processor Signals Page-Fault Exception (#PF) Instead of Alignment Check
Exception (#AC) on an Unlocked CMPXCHG8B Instruction
Exception (#AC) on an Unlocked CMPXCHG8B Instruction
Problem:
If a Page-Fault Exception (#PF) and Alignment Check Exception (#AC) both occur for an unlocked
CMPXCHG8B instruction, then #PF will be flagged.
CMPXCHG8B instruction, then #PF will be flagged.
Implication: Software that depends on the Alignment Check Exception (#AC) before the Page-Fault Exception (#PF)
will be affected since #PF is signaled in this case.
Workaround: Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the page
fault in the page fault handler and then restart the faulting instruction.
Status:
For the steppings affected, see the Summary Tables of Changes
V7.
When in No-Fill Mode the Memory Type of Large Pages are Incorrectly Forced to
Uncacheable
Uncacheable
Problem:
When the processor is operating in No-Fill Mode (CR0.CD=1), the paging hardware incorrectly forces
the memory type of large (PSE-4M and PAE-2M) pages to uncacheable (UC) memory type regardless of
the MTRR settings. By forcing the memory type of these pages to UC, load operations, which should hit
valid data in the L1 cache, are forced to load the data from system memory. Some applications will lose
the performance advantage associated with the caching permitted by other memory types.
the memory type of large (PSE-4M and PAE-2M) pages to uncacheable (UC) memory type regardless of
the MTRR settings. By forcing the memory type of these pages to UC, load operations, which should hit
valid data in the L1 cache, are forced to load the data from system memory. Some applications will lose
the performance advantage associated with the caching permitted by other memory types.
Implication: This erratum may result in some performance degradation when using no-fill mode with large pages.
Workaround: None identified
Status:
For the steppings affected, see the Summary Tables of Changes.
V8.
Processor May Hang Due to Speculative Page Walks to Non-Existent System
Memory
Memory
Problem:
A load operation that misses the Data Translation Lookaside Buffer (DTLB) will result in a page-walk.
If the page-walk loads the Page Directory Entry (PDE) from cacheable memory and that PDE load
returns data that points to a valid Page Table Entry (PTE) in uncacheable memory the processor will
access the address referenced by the PTE. If the address referenced does not exist the processor will
hang with no response from system memory.
If the page-walk loads the Page Directory Entry (PDE) from cacheable memory and that PDE load
returns data that points to a valid Page Table Entry (PTE) in uncacheable memory the processor will
access the address referenced by the PTE. If the address referenced does not exist the processor will
hang with no response from system memory.
Implication: Processor may hang due to speculative page walks to non-existent system memory.
Workaround: Page directories and page tables in UC memory space that are marked valid must point to physical
addresses that will return a data response to the processor.
Status:
For the steppings affected, see the Summary Tables of Changes.