Extreme 3804 Supplementary Manual

Advanced System Diagnostics and Troubleshooting Guide

27

Standard Ethernet Detection for Packet Errors on 
the Wire

Data transiting from one switch to another is checked for packet errors using the Ethernet Cyclic 
Redundancy Check (CRC) built into the IEEE 802.3 specification. 

As the sending switch assembles a frame, it performs a CRC calculation on the bits in that frame and 
stores the results of that calculation in the frame check sequence field of the frame. At the receiving end, 
the switch performs an identical CRC calculation and compares the result to the value stored in the 
frame check sequence field of the frame. If the two values do not match, the receiving switch assumes 
that packet data has been illegally modified between CRC calculation and CRC validation and discards 
the packet, and increments the CRC error counter in the MAC device associated with that port. In 
Extreme Networks devices, ExtremeWare polls the MAC CRC error count registers and makes that 
information available through the output of the 

show port rxerrors

 CLI command.

Extreme Networks’ Complementary Detection of Packet 
Errors Between Wires

The 802.3 Ethernet specification provides a CRC check for validation of data on the wire, but offers no 
guidance for handling data validation in the devices between the wires. Because these devices are far 
more complicated than the wires connected to them, common sense indicates the requirement for some 
mechanism for checking internal data integrity. To complement the Ethernet CRC data validation 
scheme, Extreme Networks switches implement an internal data checksum validation scheme referred 
to as the fabric checksum.

The switch fabric in a switch is essentially an extremely high-speed data path connecting multiple ports 
and using a set of programmable lookup tables to make intelligent forwarding decisions when moving 
data from point to point inside the switch. Figure 8 uses a generalized block diagram of a switch to 
illustrate data movement within a switch.

Fast path

This term refers to the data path for a packet that traverses a switch and does not 
require processing by the CPU. Fast path packets are handled entirely by ASICs 
and are forwarded at wire rate.

Slow path

This term refers to the data path for packets that must be processed by the switch 
CPU, whether they are generated by the CPU, removed from the network by the 
CPU, or simply forwarded by the CPU.

Table 3: Data Error Terms (continued)