Cisco Cisco ACE Application Control Engine Module White Paper
© 2011 Cisco and/or its affiliates. All rights reserved. This document is Cisco Public Information.
Page 26 of 40
Command Syntax and Example
Description
system watchdog memory [timeout]
switch/Admin# show system watchdog ?
lcp Show LCP watchdog status
memory Show watchdog memory status
scp Show SCP watchdog status
| Output modifiers.
> Output Redirection.
<cr> Carriage return.
lcp Show LCP watchdog status
memory Show watchdog memory status
scp Show SCP watchdog status
| Output modifiers.
> Output Redirection.
<cr> Carriage return.
switch/Admin# show system watchdog
LCP watchdog : Enabled Timeout: 20 seconds
SCP watchdog : Enabled Timeout: 13 seconds
Memory watchdog : Enabled Timeout: 90 seconds
switch/Admin# system no watchdog memory
Disabling low Memory Watchdog
switch/Admin# system no watchdog lcp
Disabling LCP Watchdog
switch/Admin# system no watchdog scp
Disabling SCP Watchdog
switch/Admin# show system watchdog
LCP watchdog : Disabled
SCP watchdog : Disabled
Memory watchdog : Disabled
LCP watchdog : Enabled Timeout: 20 seconds
SCP watchdog : Enabled Timeout: 13 seconds
Memory watchdog : Enabled Timeout: 90 seconds
switch/Admin# system no watchdog memory
Disabling low Memory Watchdog
switch/Admin# system no watchdog lcp
Disabling LCP Watchdog
switch/Admin# system no watchdog scp
Disabling SCP Watchdog
switch/Admin# show system watchdog
LCP watchdog : Disabled
SCP watchdog : Disabled
Memory watchdog : Disabled
New ACE show Commands
The Cisco ACE30 module also adds numerous show commands to aid in the operation and administration of the
Cisco ACE30 module. Table 6, provides a detailed list of the new CLI show commands. This table lists the
command, an example of how it is used, and a brief description of the new command. For IPv6 specific show
commands, please see the
module.
Table 6.
New ACE Show command and output
Command Syntax and Example
Description
show dc <0|1> controller all
switch/Admin# show dc 0 controller all
SNO Verni Register Name Address Value
0 VERNI_FPGA_REV_REG_ADDR 0x 0 0x20104
1 VERNI_FIFO32RXDYNPSREG_REG_ADDR 0x 4 0x80
2 VERNI_CFG_REG_ADDR 0x 10 0x1601
3 VERNI_CFG_OTN_REG_ADDR 0x 1c 0x0
4 VERNI_STS_REG_ADDR 0x 18 0x17f
5 VERNI_TEST_REG_ADDR 0x 20 0x0
6 VERNI_LED_CTRL_REG_ADDR 0x 30 0xf
7 VERNI_PERR_REG_ADDR 0x 70 0x0
8 VERNI_FPERR_REG_ADDR 0x 74 0x0
9 VERNI_O_ISR_REG_ADDR 0x 100 0xc60000
10 VERNI_O_IER_REG_ADDR 0x 104 0x0
11 VERNI_O_IIR_REG_ADDR 0x 108 0x0
12 VERNI_S_ISR_REG_ADDR 0x 200 0x0
13 VERNI_S_IER_REG_ADDR 0x 204 0x0
14 VERNI_S_IIR_REG_ADDR 0x 208 0x0
15 VERNI_OM_STS_REG_ADDR 0x1000 0x8
16 VERNI_OM_IER_REG_ADDR 0x1004 0x0
SNO Verni Register Name Address Value
0 VERNI_FPGA_REV_REG_ADDR 0x 0 0x20104
1 VERNI_FIFO32RXDYNPSREG_REG_ADDR 0x 4 0x80
2 VERNI_CFG_REG_ADDR 0x 10 0x1601
3 VERNI_CFG_OTN_REG_ADDR 0x 1c 0x0
4 VERNI_STS_REG_ADDR 0x 18 0x17f
5 VERNI_TEST_REG_ADDR 0x 20 0x0
6 VERNI_LED_CTRL_REG_ADDR 0x 30 0xf
7 VERNI_PERR_REG_ADDR 0x 70 0x0
8 VERNI_FPERR_REG_ADDR 0x 74 0x0
9 VERNI_O_ISR_REG_ADDR 0x 100 0xc60000
10 VERNI_O_IER_REG_ADDR 0x 104 0x0
11 VERNI_O_IIR_REG_ADDR 0x 108 0x0
12 VERNI_S_ISR_REG_ADDR 0x 200 0x0
13 VERNI_S_IER_REG_ADDR 0x 204 0x0
14 VERNI_S_IIR_REG_ADDR 0x 208 0x0
15 VERNI_OM_STS_REG_ADDR 0x1000 0x8
16 VERNI_OM_IER_REG_ADDR 0x1004 0x0
Dumps all data plane (aka verni)
register.
register.
show dc <0|1> console
switch/Admin# show dc 0 console
mCPU console is directed to base board front panel
mCPU console is directed to base board front panel
Displays whether the master or
slave CPU is directed to base board
front panel.
slave CPU is directed to base board
front panel.