Intel D525 AU80610006225AA User Manual

Datasheet

17

IGNNE#

IGNNE# (Ignore Numeric Error) is asserted to force 
the processor to ignore a numeric error and continue 
to execute non-control floating-point instructions. If 
IGNNE# is deasserted, the processor generates an 
exception on a non-control floating-point instruction 
if a previous floating-point instruction caused an 
error. IGNNE# has no effect when the NE bit in 
control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to 
ensure recognition of this signal following an Input/
Output write instruction, it must be valid along with 
the TRDY# assertion of the corresponding Input/
Output Write bus transaction.

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CMOS

INIT#

INIT# (Initialization), when asserted, resets integer 
registers inside the processor without affecting its 
internal caches or floating-point registers. The 
processor then begins execution at the power-on 
Reset vector configured during power-on 
configuration. The processor continues to handle 
snoop requests during INIT# assertion. INIT# is an 
asynchronous signal. However, to ensure recognition 
of this signal following an Input/Output Write 
instruction, it must be valid along with the TRDY# 
assertion of the corresponding Input/Output Write 
bus transaction. 

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Core

CMOS

LINT00, LINT10

LINT[1:0] (Local APIC Interrupt) must connect the 
appropriate pins of all APIC Bus agents. When the 
APIC is disabled, the LINT00 signal becomes INTR, a 
maskable interrupt request signal, and LINT10 
becomes NMI, a non-maskable interrupt. INTR and 
NMI are backward compatible with the signals of 
those names on the Pentium processor. Both signals 
are asynchronous.
Both of these signals must be software configured 
via BIOS programming of the APIC register space to 
be used either as NMI/INTR or LINT00/LINT10. 
Because the APIC is enabled by default after Reset, 
operation of these pins as LINT00/LINT10 is the 
default configuration.

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CMOS