Intel D525 AU80610006225AA User Manual

Datasheet

23

LVD_A_DATAP[2:0]

Differential data output - positive

O

LVDS

LVD_A_DATAN[2:0]

Differential data output - negative

O

LVDS

LVD_A_CLKP

Differential clock output - positive

O

LVDS

LVD_A_CLKN

Differential clock output - negative

O

LVDS

LVD_IBG

LVDS Reference Current. Need 2.37 kOhms 
pull-down resistor

I/O

Ref

LVD_VBG

Reserved. No connect.

O

Analog

LVD_VREFH

Reserved. Can be connected to V

SS

 or left as 

No Connect.

I

Ref

LVD_VREFL

Reserved. Can be connected to V

SS

 or left as 

No Connect.

I

Ref

LVDD_EN

LVDS panel power enable: Panel power control 
enable control.
This signal is also called VDD_DBL in the CPIS 
specification and is used to control the VDC 
source to the panel logic.

O

HVCMOS

LBKLT_EN

LVDS backlight enable: Panel backlight enable 
control.
This signal is also called ENA_BL in the CPIS 
specification and is used to gate power into the 
backlight circuitry.
Note: The accuracy of the PWM duty cycle of 
LBKLT_CTL signal for any given value will be 
within ±20 ns.

O

HVCMOS

LBKLT_CTL

Panel backlight brightness control: Panel 
brightness control. This signal is also called 
VARY_BL in the CPIS specification and is used 
as the PWM clock input signal. 

O

HVCMOS

LCTLA_CLK

I2C based control signal (clock) for External 
SSC clock chip control - optional

I/O

COD

LCTLB_DATA

I2C based control signal (data) for External 
SSC clock chip control - optional

I/O

COD

LDDC_CLK

Display Data Channel clock

I/O

COD

LDDC_DATA

Display Data Channel data

I/O

COD