Intel D525 AU80610006225AA User Manual
Product codes
AU80610006225AA
Datasheet
33
Functional Description
3.2.4.2
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
These signals can be polarity adjusted and individually disabled in one of the two
possible states. The sync signals should power up disabled in the high state. No
composite sync or special flat panel sync support will be included.
These signals can be polarity adjusted and individually disabled in one of the two
possible states. The sync signals should power up disabled in the high state. No
composite sync or special flat panel sync support will be included.
3.2.4.3
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
3.2.4.4
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the
host system and display. Both configuration and control information can be exchanged
allowing plug- and-play systems to be realized. Support for DDC 1 and DDC 2 is
implemented. The CPU uses the CRT_DDC_CLK and CRT_DDC_DATA signals to
communicate with the analog monitor. The CPU will generate these signals at 3.3V.
External pull-up resistors and level shifting circuitry should be implemented on the
board.
host system and display. Both configuration and control information can be exchanged
allowing plug- and-play systems to be realized. Support for DDC 1 and DDC 2 is
implemented. The CPU uses the CRT_DDC_CLK and CRT_DDC_DATA signals to
communicate with the analog monitor. The CPU will generate these signals at 3.3V.
External pull-up resistors and level shifting circuitry should be implemented on the
board.
The CPU implements a hardware GMBus controller that can be used to control these
signals allowing for transactions speeds up to 100 kHz.
signals allowing for transactions speeds up to 100 kHz.
3.2.5
Multiple Display Configurations
Microsoft Windows* 2000, Windows* XP, and Windows* Vista operating systems
provide support for multi-monitor display. The CPU supports Dual Display Clone and
Extended Desktop (LVDS + VGA).
provide support for multi-monitor display. The CPU supports Dual Display Clone and
Extended Desktop (LVDS + VGA).
3.3
Thermal Sensor
There are several registers that need to be configured to support the uncore thermal
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point as protection for the CPU. If the Catastrophic Trip Point is crossed, then the
CPU will instantly turn off all clocks inside the device. Customers may optionally enable
the Hot Trip Point to generate SMI#. Customers will be required to then write their own
SMI# handler in BIOS that will speed up the CPU (or system) fan to cool the part.
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point as protection for the CPU. If the Catastrophic Trip Point is crossed, then the
CPU will instantly turn off all clocks inside the device. Customers may optionally enable
the Hot Trip Point to generate SMI#. Customers will be required to then write their own
SMI# handler in BIOS that will speed up the CPU (or system) fan to cool the part.
3.3.1
PCI Device 0, Function 0
The SMICMD register requires that a bit be set to generate an SMI# when the Hot Trip
point is crossed. The ERRSTS register can be inspected for the SMI alert.
point is crossed. The ERRSTS register can be inspected for the SMI alert.