Intel D525 AU80610006225AA User Manual

Datasheet

41

Arbitrary connection of these signals to V

CC

*, V

SS

*, or to any other signal (including 

each other) may result in component malfunction. See 

 for a land listing of 

the processor and the location of all reserved signals. 

For reliable operation, always connect unused inputs or bi-directional signals to an 
appropriate signal level. Unused active high inputs should be connected through a 
resistor to ground (V

SS

). Unused outputs maybe left unconnected; however, this may 

interfere with some Test Access Port (TAP) functions, complicate debug probing, and 
prevent boundary scan testing. A resistor must be used when tying bi-directional 
signals to power or ground. When tying any signal to power or ground, a resistor will 
also allow for system testability. Resistor values should be within ±20% of the 
impedance of the baseboard trace, unless otherwise noted in the appropriate platform 
design guidelines.

Signals are grouped by buffer type and similar characteristics as listed in 

The buffer type indicates which signaling technology and specifications apply to the 
signals. All the differential signals, and selected DDR2 and Control Sideband signals 
have On-Die Termination (ODT) resistors. There are some signals that do not have ODT 
and need to be terminated on the board. 

All Control Sideband Asynchronous signals are required to be asserted/deasserted for 
at least eight BCLKs in order for the processor to recognize the proper signal state. See 

 for the DC and AC specifications.

Due to the voltage levels supported by other components in the Test Access Port (TAP) 
logic, Intel recommends the processor be first in the TAP chain, followed by any other 
components within the system. A translation buffer should be used to connect to the 
rest of the chain unless one of the other components is capable of accepting an input of 
the appropriate voltage. Two copies of each signal may be required with each driving a 
different voltage level. 

 specifies absolute maximum and minimum ratings. At conditions outside 

functional operation condition limits, but within absolute maximum and minimum 
ratings, neither functionality nor long-term reliability can be expected. If a device is 
returned to conditions within functional operation limits after having been subjected to 
conditions outside these limits (but within the absolute maximum and minimum 
ratings) the device may be functional, but with its lifetime degraded depending on 
exposure to conditions exceeding the functional operation condition limits.

Although the processor contains protective circuitry to resist damage from Electro-
Static Discharge (ESD), precautions should always be taken to avoid high static 
voltages or electric fields.