Intel D525 AU80610006225AA User Manual

56

Datasheet

The following are general rules for all core C-states, unless specified otherwise:

•

A core C-State is determined by the lowest numerical thread state (e.g., Thread0 
requests C0 while thread1 requests C1, resulting in a core C0 state).

•

A core transitions to C0 state when:

— an interrupt occurs.

— there is an access to the monitored address if the state was entered via an 

MWAIT instruction.

•

For core C1, an interrupt directed toward a single thread wakes only that thread. 
However, since both threads are no longer at the same core C-state, the core 
resolves to C0. 

•

Any interrupt coming into the processor package may wake any core.

The following state descriptions assume that both threads are in common low power 
state. For cases when only 1 thread is in a low power state, no change in power state 
will occur.

This is the normal operating state for the processor core. The processor core remains in 
the Normal state when the processor core is in the C0, C1/AutoHALT, or C1/MWAIT 
state. C0 is the active execution state. 

C1/AutoHALT is a low-power state entered when one thread executes the HALT 
instruction while the other is in the TC1 or greater thread state. The processor core will 
transition to the C0 state upon occurrence of SMI#, INIT#, LINT00/LINT10 (NMI, 
INTR), or internal bus interrupt messages. RSTINB will cause the processor core to 
immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal 
state or the AutoHALT power down state. See the Intel

Software Developer’s Manuals, Volume 3A/3B: System Programmer’s Guide for more 
information.

While in AutoHalt power down state, the processor core will process bus snoops. The 
processor core will enter an internal snoopable sub-state to process the snoop and then 
return to the AutoHALT power down state.

Normal (C0)

Normal (C0)

Normal (C0)

AutoHalt (C1)