Intel X3470 BV80605001905AJ User Manual

68

Datasheet, Volume 1

1.

Refer to 

 for signal description details.

2.

SA and SB refer to DDR3 Channel A and DDR3 Channel B.

3.

These signals are only used on processors and platforms that support ECC DIMMs.

4.

These signals will not be actively used on the Intel Xeon processor 3400 series. 

All Control Sideband Asynchronous signals are required to be asserted/de-asserted for 
at least eight BCLKs for the processor to recognize the proper signal state. See 

 for the DC specifications.

Single Ended

(qb)

CMOS Input

RSTIN#

Single Ended

(r)

CMOS Output

VTT_SELECT

Single Ended

(s)

CMOS Bi-directional

VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]

Single Ended

(t)

Analog Input

COMP0, COMP1, COMP2, COMP3, 

SM_RCOMP[2:0], ISENSE

Single Ended

(ta)

Analog Output

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

(u)

Power

VCC, VCC_NCTF, VTT, VCCPLL, 

VDDQ, VAXG

(v)

Ground

VSS, CGC_TP_NCTF

(w)

No Connect

RSVD, RSVD_NCTF, RSVD_TP, 

FC_x

Single Ended

(x)

Asynchronous CMOS 

Output

PSI#

(y)

Sense Points

VCC_SENSE, VSS_SENSE, 

VTT_SENSE, VSS_SENSE_VTT, 

VAXG_SENSE, VSSAXG_SENSE

(z)

Other

SKTOCC#, DBR#

Differential

(ac)

PCI Express Input

PEG_RX[15:0], PEG_RX#[15:0]

Differential

(ad)

PCI Express Output

PEG_TX[15:0], PEG_TX#[15:0]

Single Ended

(ae)

Analog Input

PEG_ICOMP0, PEG_ICOMPI, 

PEG_RCOMP0, PEG_RBIAS

Differential

(af)

DMI Input

DMI_RX[3:0], DMI_RX#[3:0]

Differential

(ag)

DMI Output

DMI_TX[3:0], DMI_TX#[3:0]

Single Ended

(ah)

FDI Input

FDI_FSYNC[1:0]

4

, 

FDI_LSYNC[1:0]

4

, FDI_INT

4

Differential

(ai)

FDI Output

FDI_TX[7:0]

4

, FDI_TX#[7:0]

4