Intel E7210 LF80564QH0568M Data Sheet

Product codes

LF80564QH0568M

Document Number: 318080-002

6.2.3

Thermal Monitor 2 ................................................................................ 104

6.2.4

On-Demand Mode................................................................................. 105

6.2.5

PROCHOT# Signal ................................................................................ 106

6.2.6

FORCEPR# Signal ................................................................................. 106

6.2.7

THERMTRIP# Signal .............................................................................. 106

6.3

Platform Environment Control Interface (PECI) .................................................... 107
6.3.1

Introduction......................................................................................... 107

6.3.2

PECI Specifications ............................................................................... 108

Features ................................................................................................................ 111
7.1

Power-On Configuration Options ........................................................................ 111

7.2

Clock Control and Low Power States................................................................... 111
7.2.1

Normal State ....................................................................................... 112

7.2.2

HALT or Extended HALT State................................................................. 112

7.2.3

Stop-Grant State .................................................................................. 114

7.2.4

Extended HALT Snoop or HALT Snoop State, Stop Grant

Snoop State......................................................................................... 115

7.3

Enhanced Intel SpeedStep® Technology............................................................. 115

7.4

System Management Bus (SMBus) Interface ....................................................... 116
7.4.1

SMBus Device Addressing ...................................................................... 117

7.4.2

PIROM and Scratch EEPROM Supported SMBus Transactions....................... 118

7.4.3

Processor Information ROM (PIROM) ....................................................... 119

7.4.4

Checksums .......................................................................................... 137

7.4.5

Scratch EEPROM ................................................................................... 137

Boxed Processor Specifications.............................................................................. 139
8.1

Introduction.................................................................................................... 139

8.2

Thermal Specifications...................................................................................... 139
8.2.1

Boxed Processor Cooling Requirements.................................................... 139

Debug Tools Specifications .................................................................................... 141
9.1

Debug Port System Requirements ...................................................................... 141

9.2

Logic Analyzer Interface (LAI) ........................................................................... 141
9.2.1

Mechanical Considerations ..................................................................... 141

9.2.2

Electrical Considerations ........................................................................ 142