Nokia 8550 Service Manual

NSM–3/3D

System Module

PAMS Technical Documentation

Page  27

Issue 4  02/2002

 Nokia Corporation

The baseband functions are controlled by the MAD asic, which consists of
a MCU, a system ASIC and a DSP.

MAD2 WD1 contains following building blocks:

 – ARM RISC processor with both 16–bit instruction set (THUMB mode)

and 32–bit instruction set (ARM mode)

 – TI Lead DSP core with peripherials:

 – API (Arm Port Interface memory) for MCU–DSP commu-

nication, DSP code download, MCU interrupt handling vec-
tors (in DSP RAM) and DSP booting.

 – Serial port (connection to PCM)

 – Timer

 – DSP memory

 – BUSC (BusController for controlling accesses from ARM to API, Sys-

tem Logic and MCU external memories, both 8– and 16–bit memories)

 – System Logic

 – CTSI (Clock, Timing, Sleep and Interrupt control)

 – MCUIF (Interface to ARM via B

US

C). Contains MCU Boo-

tROM

 – DSPIF (Interface to DSP)

 – MFI (Interface to COBBA AD/DA Converters)

 – CODER (Block encoding/decoding and A51&A52 ciphering)

 – AccIF(Accessory Interface)

 – SCU (Synthesizer Control Unit for controlling 2 separate

synthesizer)

 – UIF (Keyboard interface, serial control interface for COBBA

PCM Codec, LCD Driver and CCONT)

 – SIMI (SimCard interface with enhanched features)

 – PUP (Parallel IO, USART and PWM control unit for vibra

and buzzer)

 – Flexpool

The MAD2 operates from a 13 MHz system clock, which is generated
from the 13Mhz VCXO frequency. The MAD2 supplies a 6,5 MHz or a 13
MHz internal clock for the MCU and system logic blocks and a 13 MHz
clock for the DSP, where it is multiplied to 45.5 MHz DSP clock. The sys-
tem clock can be stopped for a system sleep mode by disabling the
VCXO supply power from the CCONT regulator output. The CCONT pro-
vides a 32 kHz sleep clock for internal use and to the MAD2, which is