Nokia 8550 Service Manual
NSM–3/3D
System Module
PAMS Technical Documentation
Page 43
Issue 4 02/2002
Nokia Corporation
Frequency synthesizer
VCO frequency is locked with PLL into stable frequency source, which is
a VCTCXO–module ( voltage controlled temperature compensated crystal
oscillator ). VCTCXO is running at 26 MHz. Temperature effect is con-
trolled with AFC ( automatic frequency control ) voltage. VCTCXO is
locked into frequency of the base station. AFC is generated by baseband
with a 11 bit conventional DAC in COBBA.
a VCTCXO–module ( voltage controlled temperature compensated crystal
oscillator ). VCTCXO is running at 26 MHz. Temperature effect is con-
trolled with AFC ( automatic frequency control ) voltage. VCTCXO is
locked into frequency of the base station. AFC is generated by baseband
with a 11 bit conventional DAC in COBBA.
PLL is located in HAGAR RF–IC and is controled via serial bus from
COBBA–IC (baseband).
COBBA–IC (baseband).
There are 64/65 (P/P+1) prescaler, N– and A–divider, reference divider,
phase detector and charge pump for the external loop filter. SHF local sig-
nal, generated by a VCO–module ( VCO = voltage controlled oscillator ),
is fed to prescaler. Prescaler is a dual modulus divider. Output of the
prescaler is fed to N– and A–divider, which produce the input to phase
detector. Phase detector compares this signal to reference signal
(200kHz), which is divided with reference divider from VCTCXO output.
Output of the phase detector is connected into charge pump, which
charges or discharges integrator capacitor in the loop filter depending on
the phase of the measured frequency compared to reference frequency.
phase detector and charge pump for the external loop filter. SHF local sig-
nal, generated by a VCO–module ( VCO = voltage controlled oscillator ),
is fed to prescaler. Prescaler is a dual modulus divider. Output of the
prescaler is fed to N– and A–divider, which produce the input to phase
detector. Phase detector compares this signal to reference signal
(200kHz), which is divided with reference divider from VCTCXO output.
Output of the phase detector is connected into charge pump, which
charges or discharges integrator capacitor in the loop filter depending on
the phase of the measured frequency compared to reference frequency.
Loop filter filters out the pulses and generates DC control voltage to VCO.
Loop filter defines step response of the PLL ( settling time ) and effects to
stability of the loop, that’s why integrator capacitor has got a resistor for
phase compensation. Other filter components are for sideband rejection.
Dividers are controlled via serial bus. SDATA is for data, SCLK is serial
clock for the bus and SENA1 is a latch enable, which stores new data into
dividers.
Loop filter defines step response of the PLL ( settling time ) and effects to
stability of the loop, that’s why integrator capacitor has got a resistor for
phase compensation. Other filter components are for sideband rejection.
Dividers are controlled via serial bus. SDATA is for data, SCLK is serial
clock for the bus and SENA1 is a latch enable, which stores new data into
dividers.
VCO
CHARGE
PUMP
PHASE
DET.
M
R
f_out
LP
Kvco
Kd
M = A(P+1) + (N–A)P=
f ref
f_out / M
freq.
reference
reference
= NP+A
AFC–controlled VCTCXO
LO–signal is generated by SHF VCO module. VCO has double frequency
in DCS1800 and x 4 frequency in EGSM compared to actual RF channel
frequency. LO signal is divided by two or four in HAGAR (depending on
system mode).
in DCS1800 and x 4 frequency in EGSM compared to actual RF channel
frequency. LO signal is divided by two or four in HAGAR (depending on
system mode).