Intel i5-2500K BX80623I52500K User Manual
Product codes
BX80623I52500K
6
Datasheet, Volume 1
Figures
®
Core™ Processor Family Desktop Platform ..................................10
Flex Memory Technology Operation ..................................................................21
2-2 PCI Express* Layering Diagram.................................................................................24
2-3 Packet Flow through the Layers.................................................................................25
2-4 PCI Express* Related Register Structures in the Processor ............................................26
2-5 PCIe Typical Operation 16 lanes Mapping....................................................................27
2-6 Processor Graphics Controller Unit Block Diagram ........................................................28
2-7 Processor Display Block Diagram ...............................................................................31
4-1 Idle Power Management Breakdown of the Processor Cores ..........................................46
4-2 Thread and Core C-State Entry and Exit .....................................................................46
4-3 Package C-State Entry and Exit .................................................................................50
7-1 Example for PECI Host-clients Connection...................................................................84
7-2 Input Device Hysteresis ...........................................................................................85
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .........................................................88
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) .......................................................89
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .........................................................90
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) .......................................................91
2-3 Packet Flow through the Layers.................................................................................25
2-4 PCI Express* Related Register Structures in the Processor ............................................26
2-5 PCIe Typical Operation 16 lanes Mapping....................................................................27
2-6 Processor Graphics Controller Unit Block Diagram ........................................................28
2-7 Processor Display Block Diagram ...............................................................................31
4-1 Idle Power Management Breakdown of the Processor Cores ..........................................46
4-2 Thread and Core C-State Entry and Exit .....................................................................46
4-3 Package C-State Entry and Exit .................................................................................50
7-1 Example for PECI Host-clients Connection...................................................................84
7-2 Input Device Hysteresis ...........................................................................................85
8-1 Socket Pinmap (Top View, Upper-Left Quadrant) .........................................................88
8-2 Socket Pinmap (Top View, Upper-Right Quadrant) .......................................................89
8-3 Socket Pinmap (Top View, Lower-Left Quadrant) .........................................................90
8-4 Socket Pinmap (Top View, Lower-Right Quadrant) .......................................................91