Toshiba 4006GAH User Manual
360050398
Toshiba Corporation Digital Media Network Company
Page 34 of 157
© 2005, Copyright TOSHIBA Corporation All Rights Reserved
10.3.4 Series resistance
Each signal has its own series resistance.
SIGNAL
SERIAL RESISTANCE VALUE
-DIOR
82Ω
-HDMARDY
HSTROBE
-DIOW
82Ω
STOP
-CS0, -CS1
82Ω
DA0,DA1,DA2
82Ω
-DMACK
82Ω
DMARQ
22Ω
INTRQ
22Ω
IORDY
-DDMARDY
DSTROBE
-DDMARDY
DSTROBE
22Ω
DD０∼DD15
33Ω
10.3.5 Signal Description
SIGNAL DIR.
PIN
DESCRIPTION
- RESET
O (*1)
1
Reset signal from the host system; It shall be active low when system is
powered-up or when voltage fault is detected.
powered-up or when voltage fault is detected.
DD 15- 0
I/O
18- 3
16 bit bi- directional data bus between the host system and the drive. All 16 bits
are used for data transfer in the data register. The lower 8 bits, HD0- HD7, are
used for the other register and ECC access.
are used for data transfer in the data register. The lower 8 bits, HD0- HD7, are
used for the other register and ECC access.
KEY
N/C
20
Pin position 20 has no connection pin, clipped on the drive and plugged on the
cable in order to ensure correct orientation of the cable and to avoid wrong
insertion.
cable in order to ensure correct orientation of the cable and to avoid wrong
insertion.
DMARQ
I
21
DMA request signal is set by the drive to indicate that the DMA data transfer is
ready. The direction of the data transfer is controlled by write/read strobe signal
(HOST IOW or HOST IOR). This signal is used on a hand shake manner with -
DMACK.
ready. The direction of the data transfer is controlled by write/read strobe signal
(HOST IOW or HOST IOR). This signal is used on a hand shake manner with -
DMACK.
- DIOW
STOP
STOP
O
23
Write strobe. The rising clocks data from the host data bus, HD0 through HD15 to
a register or data register of the drive.
Stop signal used by the host after the completion of Ultra DMA Burst.
a register or data register of the drive.
Stop signal used by the host after the completion of Ultra DMA Burst.
- DIOR
-HDMARDY
HSTROBE
-HDMARDY
HSTROBE
O
25
Read strobe. When active low, this signal enables data from a register or the data
of the drive onto the host data bus, HD0 through HD15. The rising edge of
-HOST IOR latches on the data on the bus from the drive.
This signal is for reporting the drive that the host system is ready to accept Ultra
DMA data.
Strobe. HSTROBE indicates that the host transfers ULTRA DMA data. The rising
edge and the falling edge of HSTROBE enable the drive to latch the data.
of the drive onto the host data bus, HD0 through HD15. The rising edge of
-HOST IOR latches on the data on the bus from the drive.
This signal is for reporting the drive that the host system is ready to accept Ultra
DMA data.
Strobe. HSTROBE indicates that the host transfers ULTRA DMA data. The rising
edge and the falling edge of HSTROBE enable the drive to latch the data.
IORDY
-DDMARDY
DSTROBE
-DDMARDY
DSTROBE
I
27
IORDY reports host that the BUS is available.
-DDMARDY is asserted to indicate that the drive is ready to receive the Ultra DMA
data.
Strobe. DSTROBE is asserted to indicate that the drive transfers Ultra DMA data.
The rising edge and falling edge of DSTROBE enable the host to latch the data.
-DDMARDY is asserted to indicate that the drive is ready to receive the Ultra DMA
data.
Strobe. DSTROBE is asserted to indicate that the drive transfers Ultra DMA data.
The rising edge and falling edge of DSTROBE enable the host to latch the data.