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Contec SPI-8450-LLVA User Manual

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CHAPTER 2 –Hardware Installations
 
                                                                                                                                                    
SPI-8450-LLVA
17
2.10  IDE RAID Connector: CN11/ CN12
The CPU card SPI-8450-LLVA using the chipset of Promise PDC20265R for IDE
RAID port that with the bus-mastering design takes full advantage of multi-tasking, multi-
threading operating systems and greatly improves performance.
Provides scatter/gather DMA mechanism that complies with Revision 1.0 of the
programming interface for Bus Master IDE Controller.
Scatter/Gather mechanism supports both DMA and PIO IDE drives and ATAPI
devices. Allows byte-boundary memory region during Bus Master DMA transfers which
benefits operating systems or applications, which has odd byte boundary memory transfers.
Dual independent data paths with read ahead and write posting for each channel
supported for dual IDE channels to balanced bus loading and optimal performance.
PIN No.
Function
PIN No. Function
1
RESET
2
GND
3
D7
4
D8
5
D6
6
D9
7
D5
8
D10
9
D4
10
D11
11
D3
12
D12
13
D2
14
D13
15
D1
16
D14
17
D0
18
D15
19
GND
20
N.C
21
DREQ
22
GND
23
IOW
24
GND
25
IOR
26
GND
27
IORDY
28
ALE
29
DACK
30
GND
31
IRQ
32
N.C.
33
A1
34
PDIAG
35
A0
36
A2
37
CS0
38
CS1
CN11/CN12 
 
1                2 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
39              40 
39
HD ACT
40
GND